CASTLE: Compression Architecture for Secure Low Latency, Low Energy, High Endurance NVMs

Palangappa, Poovaiah M.; Mohanram, Kartik

doi:10.1109/dac.2018.8465917

Cited by 9 publications

(7 citation statements)

References 6 publications

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“…A first group of papers related to the evaluation of reliability improvement in NV main memory or cache, focuses exclusively on measuring either the reduction in the number of writes or their variability [18,40,41]. For instance, Wang et al compare wear-leveling mechanisms in NV-LLCs by calculating the elapsed time from startup to the first bitcell fault [18].…”

Section: Forecasting the Capacity And Performance Evolution Of Nv-llcsmentioning

confidence: 99%

“…Data compression reduces the block size. This is beneficial in the NVM context because it allows fewer bits to be written and consequently extends the lifetime of the main memory or cache [33,35,40,41], or can be used to decrease the RDE rate [36]. Yet, compression has another benefit in the context of a byte-level fault tolerant NV cache such as L2C2: it allows cache frames with dead bytes to hold blocks if compression is high enough [33,39].…”

Section: Data Compressionmentioning

confidence: 99%

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L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime

et al. 2023

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Several emerging non-volatile (NV) memory technologies are rising as interesting alternatives to build the Last-Level Cache (LLC). Their advantages, compared to SRAM memory, are higher density and lower static power, but write operations wear out the bitcells to the point of eventually losing their storage capacity. In this context, this paper presents a novel LLC organization designed to extend the lifetime of the NV data array and a procedure to forecast in detail the capacity and performance of such an NV-LLC over its lifetime. From a methodological point of view, although different approaches are used in the literature to analyze the degradation of an NV-LLC, none of them allows to study in detail its temporal evolution. In this sense, this work proposes a forecasting procedure that combines detailed simulation and prediction, allowing an accurate analysis of the impact of different cache control policies and mechanisms (replacement, wear-leveling, compression, etc.) on the temporal evolution of the indices of interest, such as the effective capacity of the NV-LLC or the system IPC. We also introduce L2C2, a LLC design intended for implementation in NV memory technology that combines fault tolerance, compression, and internal write wear leveling for the first time. Compression is not used to store more blocks and increase the hit rate, but to reduce the write rate and increase the lifetime during which the cache supports near-peak performance. In addition, to support byte loss without performance drop, L2C2 inherently allows N redundant bytes to be added to each cache entry. Thus, L2C2+N, the endurance-scaled version of L2C2, allows balancing the cost of redundant capacity with the benefit of longer lifetime. For instance, as a use case, we have implemented the L2C2 cache with STT-RAM technology. It has affordable hardware overheads compared to that of a baseline NV-LLC without compression in terms of area, latency and energy consumption, and increases up to 6-37 times the time in which 50% of the effective capacity is degraded, depending on the variability in the manufacturing process. Compared to L2C2, L2C2+6 which adds 6 bytes of redundant capacity per entry, that means 9.1% of storage overhead, can increase up to 1.4-4.3 times the time in which the system gets its initial peak performance degraded.

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Section: Forecasting the Capacity And Performance Evolution Of Nv-llcsmentioning

confidence: 99%

Section: Data Compressionmentioning

confidence: 99%

L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime

et al. 2023

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“…A first group of papers related to the evaluation of reliability improvement in NV main memory or cache, focus exclusively on measuring the reduction of the number of writes or their variability [9], [27], [33]. For instance, Wang et al compare wear-leveling mechanisms in NV caches by calculating the elapsed time from startup to the first bitcell fault [33].…”

Section: B Forecasting Capacity and Performance For Nv Cachesmentioning

confidence: 99%

“…Data compression reduces the block size. This is beneficial in the NVM context because it allows fewer bits to be written and consequently extends the lifetime of the main memory or cache [7], [9], [17], [27]. Yet, compression has another benefit in the context of a byte-level fault tolerant NV cache such as L2C2: it allows cache frames with dead bytes to hold blocks if compression is high enough [12], [17].…”

Section: B Data Compressionmentioning

confidence: 99%

L2C2: Last-Level Compressed-Cache NVM and a Procedure to Forecast Performance and Lifetime

Escuin¹,

Ibáñez²,

Monreal³

et al. 2022

Preprint

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“…Counter mode encryption [3], [37], [43], [56] is commonly used for this purpose. It works by encrypting a counter to generate a pseudo one time pad (OTP) which is XORed with the plaintext (or ciphertext) to get ciphertext (or plaintext).…”

Section: B Memory Encryptionmentioning

confidence: 99%

Streamlining Integrity Tree Updates for Secure Persistent Non-Volatile Memory

Freij¹,

Yuan²,

Zhou³

et al. 2020

Preprint

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Emerging non-volatile main memory (NVMM) is rapidly being integrated into computer systems. However, NVMM is vulnerable to potential data remanence and replay attacks.Established security models including split counter mode encryption and Bonsai Merkle tree (BMT) authentication have been introduced against such data integrity attacks. However, these security methods are not readily compatible with NVMM. Recent works on secure NVMM pointed out the need for data and its metadata, including the counter, the message authentication code (MAC), and the BMT to be persisted atomically. However, memory persistency models have been overlooked for secure NVMM, which is essential for crash recoverability.In this work, we analyze the invariants that need to be ensured in order to support crash recovery for secure NVMM. We highlight that prior research has substantially under-estimated the cost of BMT persistence and propose several optimization techniques to reduce the overhead of atomically persisting updates to BMTs. The optimizations proposed explore the use of pipelining, out-of-order writes, and update coalescing while conforming to strict or epoch persistency models respectively. We evaluate our work and show that our proposed optimizations significantly reduce the performance overhead of secure NVMM with crash recoverability.

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CASTLE: Compression Architecture for Secure Low Latency, Low Energy, High Endurance NVMs

Cited by 9 publications

References 6 publications

L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime

L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime

L2C2: Last-Level Compressed-Cache NVM and a Procedure to Forecast Performance and Lifetime

Streamlining Integrity Tree Updates for Secure Persistent Non-Volatile Memory

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