Cathedral-II: A Silicon Compiler for Digital Signal Processing

Man, H. De; Rabaey, Jan M.; Six, P.; Claesen, Luc

doi:10.1109/mdt.1986.295047

Cited by 150 publications

(7 citation statements)

References 5 publications

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“…PrologueðnÞ, lengthðnÞ, and epilogueðnÞ represent corresponding execution lengths, where n is the number of resources. ListðnÞ is the execution length of a single repetitive pattern produced by the list scheduling method (Man et al, 1986), which is a simple scheduling method without the retiming technique and usually cannot obtain the optimum result. R retiming depth, dðnÞ, is the number of iterations that must be moved into the prologue and epilogue.…”

Section: Basic Principlesmentioning

confidence: 99%

A two-level scheduling method: an effective parallelizing technique for uniform nested loops on a DSP multiprocessor

Lee¹,

Chen²

2005

Journal of Systems and Software

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Section: Basic Principlesmentioning

confidence: 99%

A two-level scheduling method: an effective parallelizing technique for uniform nested loops on a DSP multiprocessor

Lee¹,

Chen²

2005

Journal of Systems and Software

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“…In the Cathedral-II system [1] the synthesis process is directed towards a similar architecture, yet they do not exploit the freedom of scheduling communications. Every value is stored in the source functional unit and communicated on a bus when it is needed, i.e.…”

Section: Related Researchmentioning

confidence: 99%

Constrained register allocation in bus architectures

Frank¹,

Raje

Sarrafzadeh

1995

Proceedings of the 32nd ACM/IEEE Conference on Design Automation Conference - DAC '95

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Partitioned memory with bus interconnect architecture in its most general form consists of several functional units with associated memory accessible to the functional unit via local interconnect and global buses to communicate data values across from one functional unit to another. As can be expected, the time at which certain values are c ommunicated aect the size of the local memories and the number of buses that are n e e ded. We address the problem of scheduling communications in a bus architecture under memory constraints. We present here a network ow formulation for the problem and obtain an exact algorithm to schedule the communications, such that the constraint on the number of registers in each functional unit is satised. As an increasing number of architectures use multiple memories in addition to (or instead of) one central RAM, this work is especially interesting. Several authors have already studied this problem in related a r chitectures, yet all use heuristic approaches to schedule the communications. Our technique is the rst exact solution to the problem. Also, our graph theoretic formulation provides a clearer insight into the problem.

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“…In certain cases, however, integration of design tasks and inferencing system, according to a fixed strategy, may be favoured. For example, Cathedral-II [8] is intended as a silicon compiler to synthesize synchronous multiprocessor system chips for digital signal processing. Because of the dedicated nature of such a design system, integration of all tasks may be more opportune.…”

Section: A Knowledge-based System In An Open Cadenvironmentmentioning

confidence: 99%

A knowledge-based approach to VLSI-design in an open CAD-environment

Alberts

Huijs

Mars

et al. 1989

Microprocessing and Microprogramming

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A knowledge-based approach is suggested to assist a designer in the increasingly complex task of generating VLSI-chips from abstract, high-level specifications of the system. The complexity of designing VLSI-circuits has reached a level where computer-based assistance has become indispensable. Not all of the design tasks allow for algorithmic solutions. AI techniques can be used, in order to support the designer with computer-aided tools for tasks not suited for algorithmic approaches. The approach described in this paper is based upon the underlying characteristics of VLSI design processes in general, comprising all stages of the design. A universal model is presented, accompanied with a recording method for the acquisition of design knowledge -strategic and task-specific -in terms of the design actions involved and their effects on the design itself. This method is illustrated by a simple design example: the implementation of the logical EXOR-component. Finally suggestions are made for obtaining a universally usable architecture of a knowledge-based system for VLSI-design. Characteristics of VLSI-designGiven a high-level, formal specification of the system, the designer of a VLSI-circuit is confronted with the problem of generating a description of the circuit that can be physically realized. Since this can not be done in a single design step, a stepwise refinement of the original description is carded out. For each design step the designer must choose among a set of alternative design actions suited for the situation. After each refinement verification of the results is needed and often some sort of optimization is performed. Depending on whether the results meet the necessary requirements, the designer will continue by selecting the next action or else he will have to reconsider the choices made. This cycle is repeated over and over, leading to a gradual refinement of the design.There are several constraints acting on the design process. On the one hand the technological and physical conditions constrain the possible design actions, as a consequence of the technology available and the characteristics of the silicon respectively. Secondly, there are a number of technical specifications that have to be met, like for example the maximum size of the final chip. The technological and physical implications are primarily bottom-up, whereas the techieal specifications work more top-down through the design process. So in effect, of only one the exact nature is known until they meet somewhere in the middle.In other words: the design process can be characterised as a complex search-process -through the intermediate design descriptions that are generated -under a number of constraints. The search is not for a single best solution, but for an acceptable compromise from a range of solutions that satisfy the requirements up to a certain degree. The complexity of this process is due to (among other things):a very large search-space, caused by the long trajectory from high-level system specification to low-level phys...

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Cathedral-II: A Silicon Compiler for Digital Signal Processing

Cited by 150 publications

References 5 publications

A two-level scheduling method: an effective parallelizing technique for uniform nested loops on a DSP multiprocessor

A two-level scheduling method: an effective parallelizing technique for uniform nested loops on a DSP multiprocessor

Constrained register allocation in bus architectures

A knowledge-based approach to VLSI-design in an open CAD-environment

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