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In the next decade, power consumption will be the dominating issue in VLSI design. Huge currents and current derivatives wall p o w in imperfect interconnections. Without careful design, this will seriously affect the timing of the chip and can even cause functional errors. Therefore high-end CMOS chips at this moment already have more than 100 power/ground pins. This paper defines in an original way the currentrelated information required t o limit the voltage drops over the imperfect interconnections. W e then present a novel linear-complezity pattern-independent solution for this problem using an intelligent hierarchy of simulators. Ileal-life examples show that the accuracy isimproved b y a factor of 2 to 5 compared to the estimates made in industrial practice.

A system is presented which automatically generates layout of bit-sliced data paths in hi h performance DSP circuits. The system consists of a mtar placement tool, a 'itrack assignment tool and detailed layout tools. In this paper we will present algorithms for linear placement of modules and routing track assi nment across the modules. By taking advantage of t fl e inherent structure of the circuits an A* based linear placement algorithm has produced better results compared to a simulated anntalmg based approach.