Estimation of typical power of synchronous CMOS circuits using a hierarchy of simulators

Vanoostende, P.; Six, P.; Vandewalle, Joos; Man, H.J. De

doi:10.1109/4.179200

Cited by 20 publications

(7 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Calculating a system's power consumption is a much more involved process than determining its area, or delay, as power is almost entirely dependent upon switching activity (for CMOS technologies), and is thus heavily tied to the data flowing through the system [14]. Estimation techniques fall into two broad categories [15]: simulationbased methods [16][17], which estimate the power consumed when a particular data set is applied to the system; and probabilistic methods [18], where an attempt is made to determine "typical" power consumption figures based on probabilistic circuit models and input activity data.…”

Section: Power Estimationmentioning

confidence: 99%

Simultaneous optimisation of dynamic power, area and delay in behavioural synthesis

Williams

Brown

Zwoliński

2000

IEE Proc., Comput. Digit. Tech.

View full text Add to dashboard Cite

Concern over power dissipation coupled with the continuing rise in system size and complexity means that there is a growing need for high-level design tools capable of automatically optimising systems to take into account power dissipation, in addition to the more conventional metrics of area, delay and testability. Current methods for reducing power consumption tend to be ad-hoc: for example, slowing down, or turning off idle parts of the system, or a controlled reduction in power supply. The behavioural synthesis system described in this paper features an integrated incremental power estimation capability, which makes use of activity profiles, generated automatically through simulation of a design on any standard VHDL simulator; accurate circuit-level cell models (generated, again automatically, via Spice simulation); and a comprehensive system power model. This data, along with similar estimators for area and delay, guides the optimisation of a design towards independent, user-specified objectives for final area, delay, clock speed, and energy consumption. In addition, a range of power reducing features are included encompassing: supply voltage scaling, clock gating, input latching, input gating, lowpower cells, and pipelined and multicycle units. These are automatically exploited during optimisation as part of the area/delay/power dissipation trade-off process. The resulting system is capable of reducing the estimated energy consumption of several benchmark designs by factors of between 3.5 and 7.0 times. Furthermore, the design exploration capability enables a range of alternative structural implementations to be generated from a single behavioural description, with differing area/delay/power trade-offs.

show abstract

Section: Power Estimationmentioning

confidence: 99%

Simultaneous optimisation of dynamic power, area and delay in behavioural synthesis

Williams

Brown

Zwoliński

2000

IEE Proc., Comput. Digit. Tech.

View full text Add to dashboard Cite

show abstract

“…Saleh [11], described an integrated simulation flow going across multiple levels and mixed domains, thus addressing the issues of interfaces, inter-domain transformation and algorithms for various analysis regimes. In [12] existing simulators at different levels of abstraction are combined in a hierarchical way in order to efficiently reduce the simulation time for accurate typical current estimation. In [14], a macro-modeling based gate-level power/timing analysis tool is described, achieving transistor level accuracy with one order of magnitude efficiency improvement.…”

Section: -Introductionmentioning

confidence: 99%

Parallel mixed-level power simulation based on spatio-temporal circuit partitioning

Chinosi¹,

Zafalon²,

Guardiani³

1999

Proceedings of the 36th Annual ACM/IEEE Design Automation Conference

View full text Add to dashboard Cite

In this work we propose a technique for spatial and temporal partitioning of a logic circuit based on the nodes activity computed by using a simulation at an higher level of abstraction. Only those components that are activated by a given input vector are added to the detailed simulation netlist. The methodology is suitable for parallel implementation on a multi-processor environment and allows to arbitrarily switch between fast and detailed levels of abstraction during the simulation run. The experimental results obtained on a significant set of benchmarks show that it is possible to obtain a considerable reduction in both CPU time and memory occupation together with a considerable degree of accuracy. Furthermore the proposed technique easily fits in the existing industrial design flows. I -INTRODUCTIONIn the last few years the complexity of electronic systems design increased exponentially, thus again outpacing the Moore's law [1]. At the same time the market pressure is leading to an equivalent fast growth of the number of functionalities integrated in a single chip, associated with always tighter performance constraints. This trend represents a considerable dilemma for the designers of portable, low-power circuits. The two dimensional (area, timing) design space is quickly expanding to a third design dimension, with power constraints becoming of primary importance for reliability, packaging cost and battery life requirements. Dynamic simulation still plays a major role for fast, accurate functional and performance analysis, but it appears to be a bottleneck in the verification flow. A huge amount of work has been done in order to improve large circuits simulation efficiency: at transistor level by exploiting relaxation [2], event driven techniques [3] and efficient device models [4]; at logical level by RTL or behavioral language modeling [5]. In the power domain, efficient power analysis tools [6], [7] and high level estimation techniques [8], [9], [10] have been introduced to overcome the complexity of the VLSI design verification problem. At the same time a generation of mixed-mode, as well as multi-domain analog simulators have also been recently introduced, improving the state of the art in this field. In [10] it is described a two level simulator for power characterization of macros in which the information available during high level simulation is exploited to reduce the number of slow, accurate low-level simulations. Saleh [11], described an integrated simulation flow going across multiple levels and mixed domains, thus addressing the issues of interfaces, inter-domain transformation and algorithms for various analysis regimes. In [12] existing simulators at different levels of abstraction are combined in a hierarchical way in order to efficiently reduce the simulation time for accurate typical current estimation. In [14], a macro-modeling based gate-level power/timing analysis tool is described, achieving transistor level accuracy with one order of magnitude efficiency improvement. Parallel simulatio...

show abstract

“…Area and performances of CMOS structures have been the subject of large investigations [1][2][3]. Power estimation of CMOS gates is considered in recent papers [4][5][6]. Due to the major difficulties in clearly defining the components involved in power estimation of CMOS structures, efforts on low power design address mostly alternatives at logical synthesis level [7].…”

Section: -Introductionmentioning

confidence: 99%

Explicit evaluation of short circuit power dissipation for CMOS logic structures

Turgis

Azémard

Auvergne

1995

Proceedings of the 1995 International Symposium on Low Power Design - ISLPED '95

View full text Add to dashboard Cite

For supply voltage standards such as Vdd > V TN + |V TP | short-circuit power dissipation significantly contributes to the total power dissipation in ICs. We propose a new alternative for the estimation of the short-circuit power dissipation, Psc, in CMOS structures. A first order calculation results in an explicit formulation for Psc, which clearly shows up the design and load parameters. Validations are performed on different configurations of inverters by comparison with HSPICE simulations. Discussions on the relative importance of short-circuit and dynamic power dissipation is given, together with considerations allowing an easy extension to gates.

show abstract

Estimation of typical power of synchronous CMOS circuits using a hierarchy of simulators

Cited by 20 publications

References 11 publications

Simultaneous optimisation of dynamic power, area and delay in behavioural synthesis

Simultaneous optimisation of dynamic power, area and delay in behavioural synthesis

Parallel mixed-level power simulation based on spatio-temporal circuit partitioning

Explicit evaluation of short circuit power dissipation for CMOS logic structures

Contact Info

Product

Resources

About