Parallel mixed-level power simulation based on spatio-temporal circuit partitioning

Abstract

In this work we propose a technique for spatial and temporal partitioning of a logic circuit based on the nodes activity computed by using a simulation at an higher level of abstraction. Only those components that are activated by a given input vector are added to the detailed simulation netlist. The methodology is suitable for parallel implementation on a multi-processor environment and allows to arbitrarily switch between fast and detailed levels of abstraction during the simulation run. The experimental results obtained on a significant set of benchmarks show that it is possible to obtain a considerable reduction in both CPU time and memory occupation together with a considerable degree of accuracy. Furthermore the proposed technique easily fits in the existing industrial design flows. I -INTRODUCTIONIn the last few years the complexity of electronic systems design increased exponentially, thus again outpacing the Moore's law [1]. At the same time the market pressure is leading to an equivalent fast growth of the number of functionalities integrated in a single chip, associated with always tighter performance constraints. This trend represents a considerable dilemma for the designers of portable, low-power circuits. The two dimensional (area, timing) design space is quickly expanding to a third design dimension, with power constraints becoming of primary importance for reliability, packaging cost and battery life requirements. Dynamic simulation still plays a major role for fast, accurate functional and performance analysis, but it appears to be a bottleneck in the verification flow. A huge amount of work has been done in order to improve large circuits simulation efficiency: at transistor level by exploiting relaxation [2], event driven techniques [3] and efficient device models [4]; at logical level by RTL or behavioral language modeling [5]. In the power domain, efficient power analysis tools [6], [7] and high level estimation techniques [8], [9], [10] have been introduced to overcome the complexity of the VLSI design verification problem. At the same time a generation of mixed-mode, as well as multi-domain analog simulators have also been recently introduced, improving the state of the art in this field. In [10] it is described a two level simulator for power characterization of macros in which the information available during high level simulation is exploited to reduce the number of slow, accurate low-level simulations. Saleh [11], described an integrated simulation flow going across multiple levels and mixed domains, thus addressing the issues of interfaces, inter-domain transformation and algorithms for various analysis regimes. In [12] existing simulators at different levels of abstraction are combined in a hierarchical way in order to efficiently reduce the simulation time for accurate typical current estimation. In [14], a macro-modeling based gate-level power/timing analysis tool is described, achieving transistor level accuracy with one order of magnitude efficiency improvement. Parallel simulatio...