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In the next decade, power consumption will be the dominating issue in VLSI design. Huge currents and current derivatives wall p o w in imperfect interconnections. Without careful design, this will seriously affect the timing of the chip and can even cause functional errors. Therefore high-end CMOS chips at this moment already have more than 100 power/ground pins. This paper defines in an original way the currentrelated information required t o limit the voltage drops over the imperfect interconnections. W e then present a novel linear-complezity pattern-independent solution for this problem using an intelligent hierarchy of simulators. Ileal-life examples show that the accuracy isimproved b y a factor of 2 to 5 compared to the estimates made in industrial practice.

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VHDL-based behavioral synthesis is appearing on the market but it still has to prove that it can have a significant impact. In the past, most applications for behavioral synthesis came from the DSP area and from the academic world. In contrast, this paper describes the results of an investigation we carried out on recent designs of Alcatel-Bell, leading to a more detailed study of 5 industrial telecom non-DSP circuits, that were suitable for behavioral synthesis.Our conclusion is that there is distinctly a market potential. However, we experienced that efficient use for telecom non-DSP circuits requires functionality that goes beyond simply generating an RTL-synthesizable description. This functionality is also discussed.