The implementation of deterministic RAM self-test algorithms turns out to be very area-consuming when a single ASIC contains many small, deeply embedded RAMs.Therefore, we have opted to reuse and modify the existing functional logic and to use a combined deterministic pseudo-random self-test strategy. A novel fault coverage dculation method for this self-test strategy has been developed. The method is easy to use because it is fully integrated in a hardware description language based design environment. Results for a chip set for broadband ISDN show that the combination of pseudo-random data generation and deterministic addressing of the RAMS provides high fault coverage results. Circuitry overhead varies between 2 and 14 percent of the RAM surface.INTERNATIONAL TEST CONFERENCE 1993 0-7803-1 429-8/93 $3.00 1993 IEEE Paper 16.2

VHDL-based behavioral synthesis is appearing on the market but it still has to prove that it can have a significant impact. In the past, most applications for behavioral synthesis came from the DSP area and from the academic world. In contrast, this paper describes the results of an investigation we carried out on recent designs of Alcatel-Bell, leading to a more detailed study of 5 industrial telecom non-DSP circuits, that were suitable for behavioral synthesis.Our conclusion is that there is distinctly a market potential. However, we experienced that efficient use for telecom non-DSP circuits requires functionality that goes beyond simply generating an RTL-synthesizable description. This functionality is also discussed.

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