CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks

Ebrahimi,; Daneshtalab, Masoud; Liljeberg,; Plosila,; Tenhunen,

doi:10.1109/date.2012.6176488

Cited by 52 publications

(32 citation statements)

References 18 publications

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“…However, when the packet injection rate increases, deterministic algorithms cannot balance the load across the links. In contrast, adaptive routing algorithms [11] [12] can avoid congested links by choosing paths with low latencies. Therefore, they can decrease the probability of passing packets through congested areas.…”

Section: Introductionmentioning

confidence: 92%

Optimized Q-learning model for distributing traffic in on-Chip Networks

Farahnakian

Ebrahimi

Daneshtalab

et al. 2012

2012 IEEE 3rd International Conference on Networked Embedded Systems for Every Application (NESEA)

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Many adaptive routing protocols have been developed for Networks -on-Chip to improve the network performance by traffic reduction. In this paper, we present an adaptive routing algorithm based upon the Q-routing, which distributes traffic by a learning method in the entire network. The learning method utilizes local and global traffic information and can select the minimum latency path to the destination. Since the routing table sizes become one of the main sources of area consumption in the Q-routing algorithm, we propose a clustering approach in order to reduce the area overhead. Furthermore, this approach improves the observability of the traffic condition. Experimental results for different traffic patterns and network loads show that the proposed method achieves significant performance improvement over the Q-routing, C-routing, DBAR and Dynamic XY algorithms.

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Section: Introductionmentioning

confidence: 92%

Optimized Q-learning model for distributing traffic in on-Chip Networks

Farahnakian

Ebrahimi

Daneshtalab

et al. 2012

2012 IEEE 3rd International Conference on Networked Embedded Systems for Every Application (NESEA)

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“…Phase 2 (line [5][6][7][8][9][10][11][12][13][14]. The priority sequence is adjusted according to the known component states.…”

Section: Frr Routing Algorithmmentioning

confidence: 99%

A Fault-Tolerant Routing Algorithm for NoC Using Farthest Reachable Routers

Wang

Huang

et al. 2013

2013 IEEE 11th International Conference on Dependable, Autonomic and Secure Computing

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As technology scaling, reliability has became one of the key challenges of Network-on-Chip (NoC). Many faulttolerant routing algorithms for NoC are developed to overcome fault components and provide reliable transmission. But proposed routing algorithms do not pay enough attention to find the shortest paths, which increases latency and power consumption. In this paper, a fault-tolerant routing algorithm using new component states diffusion method based on Farthest Reachable Router (FRR) is proposed. This algorithm can reduce latency by finding the shortest paths between source and destination routers. Experiment results verify that FRR routing algorithm can tolerate 79% fault patterns within 3 × 3 and reduce latency by 16-44% compared with FON.

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“…Several minimal/non-minimal and fully adaptive routing algorithms, based on a small number of additional virtual channels, have been proposed in [6]- [13].…”

Section: Related Workmentioning

confidence: 99%

“…Ming Li et al [9] introduced congestion-aware dynamic routing algorithm DyXY that determines output channel on the basis of congestion status of buffers of adjacent nodes. RCA [10], DAR [11], DBAR [12] and CATRA [13] are congestion-aware fully adaptive routing algorithms that use non-local congestion information to route the packet using extra hardware.…”

Section: Related Workmentioning

confidence: 99%

CARM: Congestion Adaptive Routing Method for On Chip Networks

Kumar

Laxmi

Gaur

et al. 2014

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems

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Abstract-Network-on-Chip (NoC) has emerged as a longterm and efficient on-chip communication solution for MCSoC and CMP micro-architectures to overcome bottleneck of traditional bus-based interconnects. Performance of NoC is highly dependent on routing algorithm we choose. In this paper, we present a highly adaptive and deadlock free routing algorithm for 2D mesh topology to mitigate congestion. Proposed algorithm provides a high degree of adaptiveness by allowing cycles in channel dependency graph and using one additional virtual channel along the Y dimension only. It uses all available minimal/non-minimal paths between source and destination nodes. A packet is routed along the non-minimal path only when minimal paths get congested at the neighboring nodes. Results show that proposed congestion-aware routing algorithm improves network performance by routing packets through non-congested areas.

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CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks

Cited by 52 publications

References 18 publications

Optimized Q-learning model for distributing traffic in on-Chip Networks

Optimized Q-learning model for distributing traffic in on-Chip Networks

A Fault-Tolerant Routing Algorithm for NoC Using Farthest Reachable Routers

CARM: Congestion Adaptive Routing Method for On Chip Networks

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