CD uniformity improvement by active scanner corrections

Schoot, Jan B.P. van; Noordman, O.F.J.; Vanoppen, Peter; Blok, F.J.; Yim, Donggyu; Park, Chanha; Cho, Byeong-Ho; Theeuwes, Thomas; Min, Young-Hong

doi:10.1117/12.474579

Cited by 25 publications

(15 citation statements)

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“…We assume the dose sensitivity D s to have the typical value of −2 nm/% [7] Fig. 3 shows SPICE-calculated delay values as gate lengths are varied in an inverter that is implemented in 65 nm technology with equal channel lengths of the PMOS and NMOS devices.…”

Section: Circuit Delay and Leakage Power Calculationmentioning

confidence: 99%

“…7 Thus, the design's netlist representation must be updated according to the dose maps. Using the characterized cell libraries, timing analysis is performed on the new design with the updated cell masters to identify the top-K (e.g., K = 10, 000) critical paths for the complementary dosePl (see the Appendix) process to optimize.…”

Section: A Overall Optimization Flowmentioning

confidence: 99%

“…For each grid on poly (active) layer, a variable d P i,j (d A i,j ) represents the amount of dose change in the grid. Maximum circuit delay is captured using variable a p that represents the arrival time at the output 7 When the gate lengths and widths are computed from the optimized dose maps, it is possible that the computed values do not exactly match the available drive strengths of the cell masters in the characterized cell libraries. Thus, a rounding step is needed to snap the computed gate lengths and widths to the cell masters with nearest drive strengths.…”

Section: B Summary Of the Dose Map Optimization Flowmentioning

confidence: 99%

“…Today, the DoseMapper technique is used solely (albeit very effectively, e.g., [7]) to reduce ACLV or AWLV metrics for a given integrated circuit during the manufacturing process. However, to achieve optimum device performance (e.g., clock frequency) or parametric yield (e.g., total chip leakage power), not all transistor gate CD values should necessarily be the same.…”

Section: Introductionmentioning

confidence: 99%

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Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power

Jeong

Kahng

Park

et al. 2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In sub-100 nm CMOS processes, delay and leakage power reduction continue to be among the most critical design concerns. We propose to exploit the recent availability of fine-grain exposure dose control in the step-and-scan tool to achieve both design-time (placement) and manufacturing-time (yield-aware dose mapping) optimizations of timing yield and leakage power. Our placement and dose map co-optimization can improve both timing yield and leakage power of a given design. We formulate the placement-aware dose map optimization as quadratic and quadratic constraint programs which are solved using efficient quadratic program solvers. In this paper, we mainly focus on the placement-aware dose map optimization problem; in the Appendix, we describe a complementary but less impactful dose map-aware placement optimization based on an efficient cell swapping heuristic. Experimental results show noticeable improvements in minimum cycle time without leakage power increase, or in leakage power reduction without degradation of circuit performance.

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Section: Circuit Delay and Leakage Power Calculationmentioning

confidence: 99%

Section: A Overall Optimization Flowmentioning

confidence: 99%

Section: B Summary Of the Dose Map Optimization Flowmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power

Jeong

Kahng

Park

et al. 2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Improvements to CD uniformity have been made through optimization of various lithography sequences. They include die-to-die exposure dose optimization [2], focus control [3], grid size adjustment for optical proximity correction [4], writing a multitude of shading elements inside the mask to adjust wafer level CD uniformity [5], and post-exposure bake temperature profile optimization by adjusting heater power in a multi-zone controlled bake plate [6][7][8]. Photoresist thickness variation is one of the major contributors of CD variations [9].…”

Section: Introductionmentioning

confidence: 99%

Statistical parameter evaluation for swing curves for the 1.2 μm and 1.8 μm resist thickness in CMOS photolithography process technology

Adam

Hashim

2012

2012 International Conference on Statistics in Science, Business and Engineering (ICSSBE)

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The swing curve is depending on the rotation speed of the spinner and the thickness of the photoresist. The thickness should be thick enough to prevent the unexposed area from being etched. It is also need to be uniform so that the image of the pattern to be developed later is in focus at all points on the resist surface. The variation of the photoresist thickness will impact the overall yield of the devices. In this respect, the photoresist thickness needs to be characterized carefully. Therefore, an experiment was set up to determine the right thickness and exposure time to control the critical dimension of the pattern. Photoresist coater and stepper are the main equipment used in this experiment. Positive photoresist is utilized as a pattern transfer medium and elipsometer is employed for film thickness measurement. 24 wafers are used in this experiment. The wafers are separated into 2 sets, each set which consists of 12 wafers have all the thickness variation. This to test the effect of standing resist before exposure and development to the dose-to-clear. The first set is coated, exposed and development. However, the second set is exposed and developed two days after being coated. After the wafer went through the standard cleaning procedure, the wafers were then coated using standard recipes which the spin speed ranging from 6500 to 7600 rpm in 100 rpm incremental with the designated rpm fro 1.2 µm photoresist thicknesses is in the middle. Subsequently, the photoresist thickness of each wafer is measured using elipsometer. Then, the exposure process is done by creating job that will expose the wafers in 20 by 10 arrays of small squares of open field with size 2x2 mm. The exposure is done in such a way where the exposure time will step up to the right and step down to the left from the center after each column. The center of the exposure energy time/step is 240/5. Then the graph is plotted to see the different. From the results we obtained that the minima for the dose-to-clear is at 7200 rpm where the thickness is 1.22 µm. whereby the first set and the second set of wafers produce a slight variation in clearing point.

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One step forward from run-to-run critical dimension control: Across-wafer level critical dimension control through lithography and etch process

Zhang¹,

Poolla²,

Spanos³

2008

Journal of Process Control

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CD uniformity improvement by active scanner corrections

Cited by 25 publications

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Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power

Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power

Statistical parameter evaluation for swing curves for the 1.2 μm and 1.8 μm resist thickness in CMOS photolithography process technology

One step forward from run-to-run critical dimension control: Across-wafer level critical dimension control through lithography and etch process

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CD uniformity improvement by active scanner corrections

Cited by 25 publications

References 0 publications

Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power

Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power

Statistical parameter evaluation for swing curves for the 1.2 &#x03BC;m and 1.8 &#x03BC;m resist thickness in CMOS photolithography process technology

One step forward from run-to-run critical dimension control: Across-wafer level critical dimension control through lithography and etch process

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Statistical parameter evaluation for swing curves for the 1.2 μm and 1.8 μm resist thickness in CMOS photolithography process technology