Cell based design methodology for BDD SFQ logic circuits: A high speed test and feasibility for large scale circuit applications

Yoshikawa, Nobuyuki; Yoda, K.; Hoshina, H.; Kawasaki, Kenji; Fujiwara, K.; Matsuzaki, F.; Nakajima, N.

doi:10.1109/tasc.2003.813923

Cited by 3 publications

(2 citation statements)

References 10 publications

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“…The DFFC is the important circuit component of the SFQ decoder, which is indispensable to build memory system [26][27][28]. The SFQ flip-flops with complementally outputs containing -JJs can be also applied to processing dual-rail SFQ data [29][30][31].…”

Section: Delay Flip-flop With Complementally Outputsmentioning

confidence: 99%

Simulation of the Margins in Single Flux Quantum Circuits Containing π-Shifted Josephson Junctions

Yamanashi

Nakaishi

Yoshikawa

2019

IEEE Trans. Appl. Supercond.

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We designed several single flux quantum (SFQ) flipflops and logic gates composed of Josephson junctions (JJs) and shifted JJs (-JJs) to quantitatively evaluate effectiveness of introduction of -JJs into the SFQ logic circuit. One-output flip-flops and logic gates were designed on the basis of the circuit design methodology we built for the SFQ circuit containing -JJs. The designed flip-flops and logic gates have wide operating margins, the dc bias margins of larger than ±30% and device parameter margins of ±18%, though the static power consumption are reduced compared to conventional ones composed of JJs. We found that the difference in the critical current density between JJs and -JJs does not affect the operating margins of the SFQ flip-flop composed of JJs and -JJs. We devised a circuit structure of the delay flip-flop with complementary outputs composed of JJs and -JJs (-DFFC). The analog circuit simulation shows the dc-bias margin of the -DFFC is larger than ±33%. These results indicate that the large-scale SFQ logic circuit system can be implemented using the flip-flops and logic gates containing -JJs.  Index Terms-Single-flux-quantum (SFQ) circuit, -shifted Josephson junction, flip-flop I. INTRODUCTION NERGY Consumption for Information and Communication Technology (ICT) has drastically increased for decades.Total energy consumption for ICT devices in the world has already reached 1 PWh/year in 2017, which is larger than annual energy consumption in Japan, and is estimated to keep increasing in the future [1]. However, semiconductor integrated circuit technology, which has been supporting the ICT development, is facing several obstacles [2]. Among the obstacles, power consumption is the most serious problem of the semiconductor complementary metal-oxide-semiconductor (CMOS) integrated circuit. In this sort of situation, beyond-CMOS devices that can overcome limitation of CMOS devices, have been studied [3]. Among various beyond-CMOS devices, superconducting digital devices, including single-fluxquantum (SFQ) devices [4,5] and its improved versions have a high-speed operation characteristic with ultra-high energy ef-Manuscript receipt and acceptance dates will be inserted here.

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Section: Delay Flip-flop With Complementally Outputsmentioning

confidence: 99%

Simulation of the Margins in Single Flux Quantum Circuits Containing π-Shifted Josephson Junctions

Yamanashi

Nakaishi

Yoshikawa

2019

IEEE Trans. Appl. Supercond.

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“…3 shows a block diagram of the system, which is composed of three stages of BSHS modules and a dual rail one-bit DDST half adder. In this demonstration we used the DDST half adder based on a binary decision diagram (BDD) [6], which is one way to realize DDST SFQ circuits. Passive transmission lines (PTLs) [7], [8] are used for the transfer of ACK signals from the module BSHS 3 to the BSHS 1 in order to reduce the handshaking delay.…”

Section: Implementation and High-speed Test Of A Bit Serial Hand mentioning

confidence: 99%

20 GHz Operation of Bit-Serial Handshaking Systems Using Asynchronous SFQ Logic Circuits

Ito

Kawasaki

Yoshikawa

et al. 2005

IEEE Trans. Appl. Supercond.

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Synchronous design is generally used in SFQ digital systems at present. In large-scale SFQ digital systems, however, the introduction of asynchronous design is required due to the large clock skew in the clock distribution network and complexity in the timing design at high clock rate. We have proposed a hierarchical design approach using asynchronous SFQ circuits with handshaking protocol for asynchronous data transfer. In our asynchronous approach, each circuit module is designed based on a data driven self-timed (DDST) architecture. A handshaking protocol is also used to ensure the logical ordering in data communication between the modules, where we have adopted bit-serial architecture to reduce the communication costs in handshaking. One issues in the bit-serial handshaking (BSHS) system is the synchronization of the input data when the module has multiple input ports. In this study, we have designed an SFQ BSHS system with multiple input ports, where Muller C-elements is used to synchronize the multiple input data. We have designed and implemented a BSHS half adder using NEC 2.5 kA cm 2 Nb standard process to demonstrate asynchronous addition of two input data at high speed. We have successfully confirmed its correct operation at about 20 GHz.

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Energy-Efficient Superconducting Computing—Power Budgets and Requirements

Holmes

Ripple²,

Manheimer

2013

IEEE Trans. Appl. Supercond.

476

285

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Cell based design methodology for BDD SFQ logic circuits: A high speed test and feasibility for large scale circuit applications

Cited by 3 publications

References 10 publications

Simulation of the Margins in Single Flux Quantum Circuits Containing π-Shifted Josephson Junctions

Simulation of the Margins in Single Flux Quantum Circuits Containing π-Shifted Josephson Junctions

20 GHz Operation of Bit-Serial Handshaking Systems Using Asynchronous SFQ Logic Circuits

Energy-Efficient Superconducting Computing—Power Budgets and Requirements

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