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We have proposed a cell-based design methodology for SFQ logic circuits based on a binary decision diagram (BDD) and implemented a BDD SFQ standard cell library using a Hypres Nb process. In this design methodology, any logic function can be implemented by connecting binary switches. Since the circuits are dual rail logic and don't need a global clock, difficulty in the timing design is reduced considerably. In our cell-based design approach, the cell library is composed of only five kinds of basic cells, whose circuit parameters are optimized so as to remove the inter-cell interaction. In the layout level, the cells have the identical size so that circuits can be implemented by simply embedding the basic cells. In this study we have performed an on-chip high-speed test of the BDD SFQ logic circuits. The test system consists of two four-bit data-driven self-timed (DDST) shift registers with a ladder type clock generator. We have confirmed 12 GHz operations of the BDD SFQ logic circuit. We have also examined circuit size dependence of the DC bias margin of large BDD SFQ circuits.Index Terms-Binary decision diagram, cell base design, cell library, RSFQ, superconducting circuits.

We have been developing an RSFQ-CMOS interface system. The system consists of three modules: a 1 to 32 bit DDST demultiplexer which converts a 16 Gb/s SFQ data input into a 32-channel 500 Mb/s output, asynchronous stacked-SQUID amplifiers which amplify an SFQ data input into a 5 mV voltage level output, and 77 K CMOS amplifiers which amplify a 5 mV voltage level input into a 5 V output at 500 MHz. We have implemented the asynchronous stacked-SQUID amplifier and the 77 K CMOS amplifier using the HYPRES 1 kA/cmZ Nb process and the ROHM 0.6 pm CMOS process, respectively. It was demonstrated that the 24-stage asynchronous stacked-SQUID amplifier amplifies an SFQ data input into a 2.0 mV voltage level at 600 MHz. The 77K CMOS amplifier was shown to amplify a 5 mV voltage level input into 5 V at 500 MHz from the simulation, and a 175 mV voltage input into 3.5 V at 90 MHz from the experiment.

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