Cell-based fully integrated CMOS frequency synthesizers

Mijuskovic, Dejan; Bayer, Martin; Chomicz, Thecla; Garg, Nidhi; James, F.; McEntarfer, P.; Porter, J.

doi:10.1109/4.278348

Cited by 88 publications

(23 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The divider chain uses ECL-and CML-type topologies for their wide bandwidth characteristic. The PFD is implemented based on a conventional structure similar to the one presented in [28]. By sending an "up" and a "down" current pulses to the CP during each reference cycle, the PFD dead zone is eliminated and the loop gain for small phase error is improved.…”

Section: Architecture Of the Thz Frequency Synthesizermentioning

confidence: 99%

A Silicon-Based 0.3 THz Frequency Synthesizer With Wide Locking Range

Chiang

Wang

Momeni

et al. 2014

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

Abstract-A 300 GHz frequency synthesizer incorporating a triple-push VCO with Colpitts-based active varactor (CAV) and a divider with three-phase injection is introduced. The CAV provides frequency tunability, enhances harmonic power, and buffers/injects the VCO fundamental signal from/to the divider. The locking range of the divider is vastly improved due to the fact that the three-phase injection introduces larger allowable phase change and injection power into the divider loop. Implemented in 90 nm SiGe BiCMOS, the synthesizer achieves a phase-noise of -77.8 dBc/Hz (-82.5 dBc/Hz) at 100 kHz (1 MHz) offset with a crystal reference, and an overall locking range of 280.32-303.36 GHz (7.9%).

show abstract

Section: Architecture Of the Thz Frequency Synthesizermentioning

confidence: 99%

A Silicon-Based 0.3 THz Frequency Synthesizer With Wide Locking Range

Chiang

Wang

Momeni

et al. 2014

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

show abstract

“…For a typical capacitance density in CMOS process of 1fF/µ m 2 -2fF/µ m 2 , 1nF capacitor would consume more than 0.5 mm 2 of active area, not mentioning reliability issues related to large metal surfaces of such capacitor. One of the so- lutions for this problem is use of dual path tuning technique [2,3]. Solid line on Figure 2 depicts a simplified Bode plot of amplitude response of the classical second order filter, with single zero and single pole.…”

Section: Loop Filter Integration By Dual Pathmentioning

confidence: 99%

“…Thus doubling the area occupied by two charge pump circuits, does not significantly change the total area requirements for complete PLL. The total tuning voltage has been originally combined using differential to single ended amplifier driving a tuning input of the VCO [2,3]. This solution does not require any modifications from the existing VCO, however it consumes more power and injects flicker noise from an op-amp directly to the oscillator.…”

Section: Loop Filter Integration By Dual Pathmentioning

confidence: 99%

12 MHz to 5800 MHz Fully Integrated, Dual Path Tuned, Low Jitter, LC-PLL Frequency Synthesizer

Keady

Szczepkowski

Farrell

2012

IET Irish Signals and Systems Conference (ISSC 2012)

View full text Add to dashboard Cite

-This paper presents a realised prototype of fully integrated CMOS LC-PLL frequency synthesizer. The circuit delivers a wide range of clock signals between 12 MHz and 5800 MHz, with average long term jitter of only 4 ps. The primary application of the presented circuit includes high speed series data transmission links. Low power consumption of the complete synthesizer (including bias circuitry), in the range of 50mW from dual 1.2 V/3.3 V supply, is in line with energy efficient solutions for modern electronic systems. The circuit is developed using a standard RF UMC 130 nm CMOS process reducing design time and necessity for customisation of its components. Full integration of RC loop filter is obtained using dual path tuning scheme, involving two separate charge pumps, two filter paths and specially modified LC-VCO architecture. Total synthesizer area including PLL circuitry with set of programmable frequency divider, output RF drivers, two separate VCO circuits and all auxiliary bias circuitry occupies no more than 0.7 mm 2 of active area.

show abstract

“…0 Applying negative feedback around the oscillator can utilize the noise-reduction property of feedback [5]. A survey of the architecture of delay cells shows a forward operation that the cell output voltage is normally produced directly from its input.…”

Section: Introductionmentioning

confidence: 99%

“…0 Using fklly-differential circuits to implement the oscillator [5][6][7][8], can suppress many common-mode sources of noise, such as thermal effects and powersupply variations.…”

Section: Introductionmentioning

confidence: 99%