Cell Design Methodology Based on Transmission Gate for Low-Power High-Speed Balanced XOR-XNOR Circuits in Hybrid-CMOS Logic Style

Nikoubin, Tooraj; Grailoo, Mahdieh; Mozafari, Sayyed Hasan

doi:10.1166/jolpe.2010.1099

Cited by 16 publications

(5 citation statements)

References 13 publications

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“…The following items are CDM methodology techniques and features that can make this logic style an efficient method for circuit design at the transistor level [16]- [20]:…”

Section: B Cdm Methodologymentioning

confidence: 99%

“…1.c), decreases delay and power consumption, propose circuit design using bigger structure which maintain acceptable characteristics. To date, CDM has been presented as an efficient logic style for design of 2-3 in XOR/XNOR logic gates and full adder blocks [16]- [20]. With categorization of the supergate design methodology based on the number of variables, this technique is a direct realization of the functions at transistor level using a big library of the cells, and where each cell has a function library.…”

Section: F(a B C) = Abc + Ab C + a B C + A Bcmentioning

confidence: 99%

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Fast, Area & Energy Efficient Supergate Design With Multi-Output & Multi-Functional CDM Cells

Nikoubin

basireddy

2019

IEEE Access

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Transistor network optimization is an effective way of improving the VLSI circuit design. Recent papers demonstrate the graph-based or library-based methodologies of the supergate (SG) design. This design approach is the direct design of the functions at the transistor level that can provide circuits with fewer transistors when compared with the conventional methods. In addition to the transistor count, the symmetry structure of the circuit, the number of transistors on the critical path, and multi-outputs and multifunctional cells are considered in this paper, as the three crucial parameters for the efficient SG cell design. Thus, the cell design methodology (CDM) logic style is used as a new approach for the SG design with some changes in the design flow for improving circuit characteristics. The proposed CDM-SG design methodology can produce a single output, complementary output, and multi-functional output SG cells. The comparison of the proposed CDM-SG cells with conventional SG cells shows a significant improvement on the layout area, power and energy consumption, and speed. The proposed CDM-SG cells with spiral structure are multioutput and multi-functional cells, which can significantly improve the circuit characteristics by improving the number of output functions over the cell area. INDEX TERMS Supergate design methodology, cell design methodology, energy-power-area efficient, SP&NSP transistor network, graph-based CDM.

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“…The following items are CDM methodology techniques and features that can make this logic style an efficient method for circuit design at the transistor level [16]- [20]:…”

Section: B Cdm Methodologymentioning

confidence: 99%

Section: F(a B C) = Abc + Ab C + a B C + A Bcmentioning

confidence: 99%

Fast, Area & Energy Efficient Supergate Design With Multi-Output & Multi-Functional CDM Cells

Nikoubin

basireddy

2019

IEEE Access

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“…They do not follow a systematic approach, whereas new solutions often have improved few characteristics, and so there is a free space for the systematic design methodology. CDM has been utilized to design some limited functions [7]- [9]. In this brief, CDM is matured as SCDM for designing three-input XOR/XNOR.…”

Section: Previous Workmentioning

confidence: 99%

“…The selection is meditated to determine dominant mechanisms and cells, in terms of PDP, power, and delay when the optimization goal is PDP. The results are used to produce To reduce complexity, we have also considered the central part of EBC and to achieve real results, the circuits have been simulated in the chain test bench [7]. The circuits have been named with the abbreviation of the mechanism (or cell) being utilized, while the other circumstances, cells, or mechanisms are assumed to be fixed.…”

Section: B Wisely Selection Of Mechanisms and Cells Based On Design mentioning

confidence: 99%

“…It also picks circuit components wisely and does not postpone the determination of the circuit characteristics after simulation. Cell design methodology (CDM) has been presented to design some limited functions, such as two-input XOR/XNOR and carry-inversecarry in the hybrid-CMOS style [7]- [9]. The predominant results persuade us to improve CDM through two stages: 1) generating more complex functions and 2) rectifying some remaining flaws.…”

Section: Introductionmentioning

confidence: 99%

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Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology

Nikoubin

Grailoo

2016

IEEE Trans. VLSI Syst.

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In this brief, we propose three efficient three-input XOR/XNOR circuits as the most significant blocks of digital systems with a new systematic cell design methodology (SCDM) in hybrid-CMOS logic style. SCDM, which is an extension of CDM, plays the essential role in designing efficient circuits. At first, it is deliberately given priority to general design goals in a base structure of circuits. This structure is generated systematically by employing binary decision diagram. After that, concerning high flexibility in design targets, SCDM aims to specific ones in the remaining three steps, which are wise selections of basic cells and amend mechanisms, as well as transistor sizing. In the end, the resultant three-input XOR/XNORs enjoy full-swing and fairly balanced outputs. They perform well with supply voltage scaling, and their critical path contains only two transistors. They also outperform their counterparts exhibiting 27%-77% reduction in average energy-delay product in HSPICE simulation based on TSMC 0.13-µm technology. The symmetric schematic topologies significantly simplify and minimize the layout, as 26%-32% improvement in area is demonstrated.Index Terms-Binary decision diagram applications, energy efficiency, hybrid-CMOS logic style, systematic design methodology, three-input XOR/XNOR circuits.

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An efficient multiplier by pass transistor logic partial product and a modified hybrid full adder for image processing applications

Rafiee

Pesaran

Sadeghi

et al. 2021

Microelectronics Journal

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Cell Design Methodology Based on Transmission Gate for Low-Power High-Speed Balanced XOR-XNOR Circuits in Hybrid-CMOS Logic Style

Cited by 16 publications

References 13 publications

Fast, Area & Energy Efficient Supergate Design With Multi-Output & Multi-Functional CDM Cells

Fast, Area & Energy Efficient Supergate Design With Multi-Output & Multi-Functional CDM Cells

Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology

An efficient multiplier by pass transistor logic partial product and a modified hybrid full adder for image processing applications

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