Cell design methodology (CDM) for balanced Carry–InverseCarry circuits in hybrid-CMOS logic style

Nikoubin, Tooraj; Grailoo, Mahdieh; Li, Changzhi

doi:10.1080/00207217.2013.832389

Cited by 6 publications

(3 citation statements)

References 19 publications

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“…CDM has the potential to be used for both of these methods. SCDM is the design methodology which can systematically generate elementary basic cells (EBC) using a binary decision diagram (BDD), and wisely choose circuit components based on specific targets [18], [19]. This takes place when mentioned features are not considered in the regular CDM.…”

Section: B Cdm Methodologymentioning

confidence: 99%

Fast, Area & Energy Efficient Supergate Design With Multi-Output & Multi-Functional CDM Cells

Nikoubin

basireddy

2019

IEEE Access

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Transistor network optimization is an effective way of improving the VLSI circuit design. Recent papers demonstrate the graph-based or library-based methodologies of the supergate (SG) design. This design approach is the direct design of the functions at the transistor level that can provide circuits with fewer transistors when compared with the conventional methods. In addition to the transistor count, the symmetry structure of the circuit, the number of transistors on the critical path, and multi-outputs and multifunctional cells are considered in this paper, as the three crucial parameters for the efficient SG cell design. Thus, the cell design methodology (CDM) logic style is used as a new approach for the SG design with some changes in the design flow for improving circuit characteristics. The proposed CDM-SG design methodology can produce a single output, complementary output, and multi-functional output SG cells. The comparison of the proposed CDM-SG cells with conventional SG cells shows a significant improvement on the layout area, power and energy consumption, and speed. The proposed CDM-SG cells with spiral structure are multioutput and multi-functional cells, which can significantly improve the circuit characteristics by improving the number of output functions over the cell area. INDEX TERMS Supergate design methodology, cell design methodology, energy-power-area efficient, SP&NSP transistor network, graph-based CDM.

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Section: B Cdm Methodologymentioning

confidence: 99%

Fast, Area & Energy Efficient Supergate Design With Multi-Output & Multi-Functional CDM Cells

Nikoubin

basireddy

2019

IEEE Access

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“…They do not follow a systematic approach, whereas new solutions often have improved few characteristics, and so there is a free space for the systematic design methodology. CDM has been utilized to design some limited functions [7]- [9]. In this brief, CDM is matured as SCDM for designing three-input XOR/XNOR.…”

Section: Previous Workmentioning

confidence: 99%

“…It also picks circuit components wisely and does not postpone the determination of the circuit characteristics after simulation. Cell design methodology (CDM) has been presented to design some limited functions, such as two-input XOR/XNOR and carry-inversecarry in the hybrid-CMOS style [7]- [9]. The predominant results persuade us to improve CDM through two stages: 1) generating more complex functions and 2) rectifying some remaining flaws.…”

Section: Introductionmentioning

confidence: 99%

Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology

Nikoubin

Grailoo

2016

IEEE Trans. VLSI Syst.

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In this brief, we propose three efficient three-input XOR/XNOR circuits as the most significant blocks of digital systems with a new systematic cell design methodology (SCDM) in hybrid-CMOS logic style. SCDM, which is an extension of CDM, plays the essential role in designing efficient circuits. At first, it is deliberately given priority to general design goals in a base structure of circuits. This structure is generated systematically by employing binary decision diagram. After that, concerning high flexibility in design targets, SCDM aims to specific ones in the remaining three steps, which are wise selections of basic cells and amend mechanisms, as well as transistor sizing. In the end, the resultant three-input XOR/XNORs enjoy full-swing and fairly balanced outputs. They perform well with supply voltage scaling, and their critical path contains only two transistors. They also outperform their counterparts exhibiting 27%-77% reduction in average energy-delay product in HSPICE simulation based on TSMC 0.13-µm technology. The symmetric schematic topologies significantly simplify and minimize the layout, as 26%-32% improvement in area is demonstrated.Index Terms-Binary decision diagram applications, energy efficiency, hybrid-CMOS logic style, systematic design methodology, three-input XOR/XNOR circuits.

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CNTFET full-adders for energy-efficient arithmetic applications

Grailoo

Hashemi

Haghshenas

et al. 2015

2015 6th International Conference on Computing, Communication and Networking Technologies (ICCCNT)

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Cell design methodology (CDM) for balanced Carry–InverseCarry circuits in hybrid-CMOS logic style

Cited by 6 publications

References 19 publications

Fast, Area & Energy Efficient Supergate Design With Multi-Output & Multi-Functional CDM Cells

Fast, Area & Energy Efficient Supergate Design With Multi-Output & Multi-Functional CDM Cells

Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology

CNTFET full-adders for energy-efficient arithmetic applications

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