Cellular arrays for asynchronous control

Patil, Suhas S.

doi:10.1145/800118.803858

Cited by 8 publications

(2 citation statements)

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“…In version 4, PC-cycle takes 109.0ns and execution of Arithmetic operation takes 100.0ns. At the second stage, the labeled petri nets are translated to asynchronous circuits where the translation method employed was inspired from Patil's work [78].…”

Section: ) Asynchronous Processor Based On Petri Netsmentioning

confidence: 99%

Towards Designing Asynchronous Microprocessors: From Specification to Tape-Out

et al. 2019

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Proceeding miniaturization in the VLSI circuits continues to pose challenges to the conventionally used synchronous design style in microprocessors. These include the distribution of clock in the GHz range, robustness to delay variations, reduction in electromagnetic interference, and energy conservation, to name a few. The asynchronous logic has been known for its ability to address the aforementioned challenges by means of the closed-loop handshake protocols, instead of notorious clock signals. Because of these advantages, there have been numerous attempts on building general and special purpose microprocessors during the last three decades. Still, however, the number of asynchronous processors commercially available is scarce, mainly due to an insufficient electronic design and automation tools support, an ambiguous design flow and testing mechanisms for asynchronous logic and, most importantly, absence of a forum to look for relevant works, explaining the design steps and tools for such microprocessors. This paper is intended to bridge this gap by 1) reviewing the design principles of asynchronous logic, including classification, signaling conventions, and pipelining approaches; 2) presenting the complete design flow and available electronic design and automation tools; 3) developing an encyclopedia of various general and special purpose microprocessors proposed by far; and 4) presenting an evaluation of those works in terms of area on the die and performance metrics. This paper will also serve as guidelines for the asynchronous microprocessor design and implementation in all phases from specification to tape-out.INDEX TERMS Asynchronous logic, electronic design and automation, microprocessor.

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Section: ) Asynchronous Processor Based On Petri Netsmentioning

confidence: 99%

Towards Designing Asynchronous Microprocessors: From Specification to Tape-Out

et al. 2019

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show abstract

“…The latter is an extension of PatilÕs mapping. He used six elements and eight modules composed of these elements to represent Petri net structures [24][25][26] . This extension, uses a seventh component, named decision-wait, that allows the synchronization of events in different groups of mutually exclusive signals.…”

Section: Techniquesmentioning

confidence: 99%