Ch’i: Scaling Microkernel Capabilities in Cache-Incoherent Systems

Ren, Yuxin; Parmer, Gabriel; Milojičić, Dejan

doi:10.1109/ross51935.2020.00007

Cited by 4 publications

References 35 publications

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Sharing non‐cache‐coherent memory with bounded incoherence

Ren

Parmer

Milojičić

2021

Concurrency and Computation

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Summary Cache coherence in modern computer architectures enables easier programming by sharing data across multiple processors. Unfortunately, it can also limit scalability due to cache coherency traffic initiated by competing memory accesses. Rack‐scale systems introduce shared memory across a whole rack, but without inter‐node cache coherence. This poses memory management and concurrency control challenges for applications that must explicitly manage cache‐lines. To fully utilize rack‐scale systems for low‐latency and scalable computation, applications need to maintain cached memory accesses in spite of non‐coherency. This paper introduces Bounded Incoherence, a memory consistency model that enables cached access to shared data‐structures in non‐cache‐coherency memory. It ensures that updates to memory on one node are visible within at most a bounded amount of time on all other nodes. We evaluate this memory model on modified PowerGraph graph processing framework, and boost its performance by 30% with eight sockets by enabling cached‐access to data‐structures.

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