Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

Khakifirooz, A.; Cheng, Kangguo; Kulkarni, P.; Cai, Jin; Ponoth, S.; Kuss, J.; Haran, B.; Kimball, A. S.; Edge, L. F.; Reznicek, A.; Adam, Thomas; He, Hongyu; Loubet, N.; Mehta, S.; Kanakasabapathy, S.; Schmitz, Stefan; Holmes, Steven J.; Jagannathan, B.; Majumdar, Amlan; Yang, Dominic C.; Upham, A.; Seo, S.-C.; Herman, J.; Johnson, Rob; Zhu, Yu; Jamison, P.; Zhu, Zhengmao; Vanamurth, L. H.; Faltermeier, J.; Fan, Songtao; Horak, D.; Bu, H.; Sadana, D. K.; Kozlowski, P.; McHerron, D.; O'Neill, J.; Doris, B.; Haensch, Wilfried; Leobondung, E.; Shahidi, G.

doi:10.1109/vtsa.2010.5488928

Cited by 26 publications

(14 citation statements)

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“…A very tight criterion of ± 5 Å has been established for the maximum tolerable peak-to-peak fl uctuation in T Si , to maintain low V TH variability. 45 Present day SOI wafer manufacturing technologies already demonstrate the route to an excellent control of T Si within this desired range. 46 Still, it should be kept in mind that the SOI wafer is subsequently thinned during the device processing steps, to obtain the target sub-10 nm body thickness.…”

Section: Evidence Of High Immunity To Statistical Variabilitymentioning

confidence: 99%

Understanding variability in complementary metal oxide semiconductor (CMOS) devices manufactured using silicon-on-insulator (SOI) technology

Markov

Cheng

Zain

et al. 2014

Silicon-on-Insulator (SOI) Technology

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Section: Evidence Of High Immunity To Statistical Variabilitymentioning

confidence: 99%

Understanding variability in complementary metal oxide semiconductor (CMOS) devices manufactured using silicon-on-insulator (SOI) technology

Markov

Cheng

Zain

et al. 2014

Silicon-on-Insulator (SOI) Technology

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“…As a result, the total measured C gg does not scale proportionally to L g . It is worth to point out that the process was not optimized for RF applications and techniques used for extrinsic C gg reduction (e.g., faceted raised source/drain ) were not employed.…”

Section: Ultrathin Body and Thin Boxmentioning

confidence: 99%

Silicon‐on‐insulator MOSFETs models in analog/RF domain

Raskin

2013

Int J Numerical Modelling

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SUMMARYSeveral physical phenomena specific to silicon-on-insulator metal-oxide-semiconductor field-effect transistors, such as floating body effects, self-heating, and substrate coupling, are described and modeled. Small-signal equivalent circuit of ultra-thin body and thin buried oxide and fin field effect transistor (FinFET) are extracted, and their radio frequency figures of merit as well as their advantages and limitations are presented. We demonstrate the importance of performing wideband characterization at the early stage of the technology development in order to identify the device weaknesses and come up with technological solutions to overcome those. With the ongoing downscaling of the metal-oxide-semiconductor devices, the surrounding of the transistor, that is, the contacts, the access lines, and the substrate, starts to play a major role on the transistor behavior. There is an urgent need to develop adequate models for the new generation of devices valid over a wide frequency band.

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“…[3,4] From circuit and device considerations the maximum T Si fluctuation that can be tolerated is < 1nm within-wafer (WiW), total wafer range of the T Si non uniformity, and wafer-to-wafer (WtW), T Si reproducibility. This translates in a SOI T Si thickness maximum wafer-to-wafer variation of 5 Å.…”

Section: Thickness Control Requirementmentioning

confidence: 99%

Excellent silicon thickness uniformity on Ultra-Thin SOI for controlling Vt variation of FDSOI

Schwarzenbach

Cauchy

Boedt

et al. 2011

2011 IEEE International Conference on IC Design &Amp; Technology

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Thickness uniformity of the Ultra Thin SOI (UTSOI) substrates is one of the key criteria to control Vt variation of the planar FDSOI devices. We present an evolutionary approach to SmartCut TM technology which already allows achieving a maximum total SOI layer thickness variation of less than  10 Å on preproduction volume. Total thickness variation of  5 Å is targeted. SUBSTRATE REQUIREMENT FOR NEXT TECHNOLOGY NODESFor the future 20nm node, standard bulk CMOS technology is facing critical tradeoffs due to increasing random dopant fluctuation, i.e. increasing threshold voltage V T statistical variability. There is consensus in the IC industry that fully depleted (FD) devices with undoped channel, also known as Ultra Thin Body (UTB) devices [1], are effective solution for eliminating random dopant fluctuation (RDF) in the MOSFET channel, thus significantly reducing threshold voltage V T variability by over 60% [2].The foundation of the FD technology is the Ultra Thin SOI (UTSOI) substrate. The starting ultra thin Si thickness (UTSOI) has to be matched to the subsequent FD CMOS processing. Clean, oxidation and etch remove few Si monolayers and it has to be taken into account when specifying the initial UTSOI thickness. The targeted channel Si thickness is typically between 6nm -7nm for 25nm gate length transistor [2]. The starting UTSOI wafers exhibit SOI layer down to 10 nm and buried oxide layer from 145nm down to 10 nm.For FD devices the total random V T variability is the result of gate line edge roughness (LER), workfunction variability and of the channel Si thickness. Since the channel is undoped, there is no significant RDF contribution to V T variability.Thus, the thickness uniformity is a key parameter to avoid additional V T variation of the planar FDSOI device. Typical uniformity requirements include on-wafer uniformity and wafer-towafer uniformity. Both of them combined are classified as layer total thickness variation (LTTV) and define the overall manufacturing process window for thickness uniformity. LTTV has to be achieved at the sub-nanometer range for the UTSOI layer for all wafers and all sites in order to meet the FD specifications. UTSOI substrates target high volume production by second half of 2011 to enable the readiness of a 20nm FD CMOS technology platform. THICKNESS CONTROL REQUIREMENTKakhifirooz et al, have shown an empirical correspondence between V T variation on FD-SOI devices and SOI layer thickness variations. [3,4] From circuit and device considerations the maximum T Si fluctuation that can be tolerated is < 1nm within-wafer (WiW), total wafer range of the T Si non uniformity, and wafer-to-wafer (WtW), T Si reproducibility. This translates in a SOI T Si thickness maximum wafer-to-wafer variation of 5 Å.

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Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

Cited by 26 publications

References 0 publications

Understanding variability in complementary metal oxide semiconductor (CMOS) devices manufactured using silicon-on-insulator (SOI) technology

Understanding variability in complementary metal oxide semiconductor (CMOS) devices manufactured using silicon-on-insulator (SOI) technology

Silicon‐on‐insulator MOSFETs models in analog/RF domain

Excellent silicon thickness uniformity on Ultra-Thin SOI for controlling Vt variation of FDSOI

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