Challenges in sleep transistor design and implementation in low-power designs

Shi, Kaijian; Howard, David

doi:10.1145/1146909.1146943

Cited by 98 publications

(52 citation statements)

References 7 publications

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“…This has almost no effect on timing if activity is within 20%. Note that more accurate sleep transistor sizing can be performed to improve the efficiency of power gating [17]; however, we don't investigate this in this paper.…”

Section: A Experimental Setupmentioning

confidence: 99%

An FPGA with power-gated switch blocks

Bsoul

Wilton

2012

2012 International Conference on Field-Programmable Technology

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Abstract-Static power consumption is an important component of the total power consumption in FPGAs built using 90 nm and smaller technology nodes. A previous study proposed powering down regions of logic blocks in an FPGA when idle to reduce the static power dissipation. This previous work did not consider powering down the switch blocks (SBs). However, the static power of SBs constitute more than 50% of an FPGA's static power. In this paper, we present an architecture that enables selectively powering down SBs along with the logic blocks during their idle periods. The potential power savings from this architecture depends on the proportion of SBs that can be powered down. We present modifications to our CAD flow to maximize the number of such SBs, and we experimentally estimate their proportion using a set of synthetic benchmark circuits. Our estimation results show that 53% to 83% of the SBs can be powered down in a functional module of size 24 × 24 tiles and an architecture power gating regions of size 4×4 tiles, leading to overall static power reductions of 70% to 84% compared to an architecture that does not support power gating.

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Section: A Experimental Setupmentioning

confidence: 99%

An FPGA with power-gated switch blocks

Bsoul

Wilton

2012

2012 International Conference on Field-Programmable Technology

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“…Recently, row-based approach has been proposed in [11] in which dedicated rows are inserted for placing sleep transistors. However, the most common sleep transistor architecture is a grid [12]. Such an implementation reduces the effects of process variation and introduces less IR drop variation [8].…”

Section: Sleep Transistor Placementmentioning

confidence: 99%

Early detection of current hot spots in power gated designs

Sengupta¹,

Ergin²,

Veneris³

2013

International Symposium on Low Power Electronics and Design (ISLPED)

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Abstract-With the growing popularity of hand-held batterypowered devices, leakage power is a major concern in the nanometer CMOS era. Power gating technique is an effective and widely adopted solution to this problem. The challenge of implementing power gating is the sizing and placement of the sleep transistors that are used to gate the power supply. In a placed design, due to non-uniform current demand of logic cells, some regions of the chip can have sleep transistors with very high current demand, causing power grid noise violations. Identifying these regions early in the design cycle is critical to the success of power gating implementation. This paper presents a novel methodology to calculate the current demand of each sleep transistor and locate regions in the chip where multiple sleep transistors experience very high current demand. In this paper, we model the spatial locality of the current drawn by each logic cells in the form of a bounding box. We explore techniques to identify the appropriate size of the bounding boxes. Furthermore, we extend the current distribution technique to handle placement blockages that do not share the sleep transistor network of the chip. Experimental results on industrial circuits show that the proposed algorithm can identify over 90% of such regions with a 20x run-time reduction compared to state-of-the-art commercial CAD tool.

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“…However, the authors did not address the issues at design/block level and on how one can achieve optimum savings by trading different parameters, such as performance degradation and area. In [4], the authors define the efficiency of power-gating and show how the efficiency varies with different design metrics, such as sleep transistor area, length and also throw light on methodologies, which can be used for sleep transistor power-mode transition. However, the authors do not provide substantial results on real circuits.…”

Section: Figures Of Merit For Power-gatingmentioning

confidence: 99%