Challenges of power electronic packaging and modeling

Liu, Yong; Kinzer, D.

doi:10.1109/esime.2011.5765799

Cited by 22 publications

(3 citation statements)

References 19 publications

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“…However, like with most copper wire bonding approaches, this has the risk of damaging the die due to excessive bonding force/energy [36]. Ribbon bonding does not, however, solve the problem of connecting the gate pad of a SiC MOSFET.…”

Section: Wire Bondless Packaging-the Road Forward?mentioning

confidence: 99%

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High Performance Silicon Carbide Power Packaging—Past Trends, Present Practices, and Future Directions

Seal

Mantooth

2017

Energies

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This paper presents a vision for the future of 3D packaging and integration of silicon carbide (SiC) power modules. Several major achievements and novel architectures in SiC modules from the past and present have been highlighted. Having considered these advancements, the major technology barriers preventing SiC power devices from performing to their fullest ability were identified. 3D wire bondless approaches adopted for enhancing the performance of silicon power modules were surveyed, and their merits were assessed to serve as a vision for the future of SiC power packaging. Current efforts pursuing 3D wire bondless SiC power modules were described, and the concept for a novel SiC power module was discussed.

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Section: Wire Bondless Packaging-the Road Forward?mentioning

confidence: 99%

“…In their 2011 paper summarizing the challenges in power packaging, Liu and Kinzer [36] from Fairchild Semiconductor hailed SiC as a foreseeable future replacement for silicon power devices. However, they agreed that the interconnection scheme had to improve.…”

Section: Wire Bondless Packaging-the Road Forward?mentioning

confidence: 99%

High Performance Silicon Carbide Power Packaging—Past Trends, Present Practices, and Future Directions

Seal

Mantooth

2017

Energies

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“…The structure of the power modules usually contains the IGBTs/Mosfets, IC dice, and passive components [1], [2]. For such system in package, generally more than 20 I/O pins are required, with pins for power I/Os at one side, and pins for IC I/Os at the other side [3], [4], [5].…”

Section: Introductionmentioning

confidence: 99%

Parameter optimization in assembly manufacturing process for a power module

Liu

2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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In this paper, the trimming process in manufacture of a power module is investigated by using the commercial FE code Ansys/LSdyna®. The setup of the trimming process consists of an automated system of cutting die, stripper, punch, and etc. The design and interworking of these tools are quite critical. On one hand, when the gap between the punch and stripper/cutting die is too big, the dambar may not be fully cut as expected. On the other hand, when the gap is too small, the punch might be broken after some cycles due to flash contamination on the tools. If the stripper clamp is too close to the package body, high stress might be generated in the package edge or even in the silicon chips to induce package crack or die crack. The DoE legs with regard to the gap between the punch & stripper and the distance between the stripper clamp & the package body are conducted by the FE dynamic simulations. The simulation results provide good guidance for the assembly process parameter setting. .

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