Characterisation and Analysis of Schottky-Tube FET exhibiting Superior Characteristic Parameters

Sharma, Swati; Goel, Anubha; Rewari, Sonam; Nath, Vandana; Gupta, Rashmi

doi:10.1007/s13369-022-07200-x

Cited by 5 publications

(5 citation statements)

References 27 publications

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“…The International Roadmap for Semiconductors is used for selecting the associated parameters for designing and the power supply voltage in the simulation. 33 The metallic source and drain regions are made of Manganese having work function ф S/D = 4.1 eV. The channel is divided into four diverse doping profiles, where the source side is highly doped (N A I = 1 Â 10 18 cm À3 ), and the drain side is lightly doped (N A IV = 1 Â 10 15 cm À3 ), the doping concentration of the middle regions of channel N A II and N A III is taken as 1 Â 10 17 cm À3 and 1 Â 10 16 cm À3 , respectively.…”

Section: Device Structure Simulation and Fabricationmentioning

confidence: 99%

“…Figure 1 illustrates the 2D structural assessment of the Non‐Uniformly Doped Dual Metal High‐K Schottky nanowire FET(NUD‐DM‐HK‐SNWFET). The International Roadmap for Semiconductors is used for selecting the associated parameters for designing and the power supply voltage in the simulation 33 . The metallic source and drain regions are made of Manganese having work function ф S/D = 4.1 eV.…”

Section: Device Structure Simulation and Fabricationmentioning

confidence: 99%

“…The Equation (1) stated Poisson's equation for NUD‐DM‐HK‐SNWFET in cylindrical coordinates as 33 :

\frac{1}{r} \frac{\partial}{\partial r} (r \frac{\partial}{\partial r} ψ_{i} (r . z)) + \frac{\partial^{2}}{\partial z^{2}} ψ_{i} (r, z) = \frac{{qN}_{A}}{ε_{s}}

…”

Section: Analytical Modelmentioning

confidence: 99%

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Analytical analysis and linearity performance of dual metalhigh‐KSchottky nanowireFET(DM‐HK‐SNWFET)

Sharma

Nath

Deswal³

et al. 2023

Int J Numerical Modelling

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This study's objectives are to deliver a relative analysis of non‐uniformly doped (NUD) and uniformly doped Dual Metal High‐K Schottky nanowire FET (DM‐HK‐SNWFET). Surface potential, subthreshold current, subthreshold swing, and drain current have been expressed and analyzed by resolving 2D Poisson's equation with suitable boundary conditions. The analog performance of the device is verified by examining cut‐off frequency (fT), trans‐conductance frequency product (TFP), gain frequency product (GFP), and gain trans‐conductance frequency product (GTFP). The results show suitable RF circuit parameters with a high switching ratio (≈3 × 109) and low subthreshold swing (61 mV/decade) for NUD‐DM‐HK‐SNWFET. Additionally, linearity frequency of merits (FOMs) and distortion performance are also studied by numerically calculating higher order voltage and current intercept point (VIP2, VIP3, IIP3, IMD3); 1‐dB compression point and Harmonics distortions (HD2 and HD3) using transconductance (gm1) along with its higher derivatives gm2 and gm3. These parameters exhibit high‐level linearity and low‐level distortion at zero crossover points in NUD‐DM‐HK‐SNWFET, making it a better contender for low‐power and high‐performance applications.

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Section: Device Structure Simulation and Fabricationmentioning

confidence: 99%

Section: Device Structure Simulation and Fabricationmentioning

confidence: 99%

See 1 more Smart Citation

Analytical analysis and linearity performance of dual metalhigh‐KSchottky nanowireFET(DM‐HK‐SNWFET)

Sharma

Nath

Deswal³

et al. 2023

Int J Numerical Modelling

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“…The dual material gate [4] and triple material gate [5] FinFET was also developed to control the SCEs. Further nanoscale devices with gates surrounding the channel on all sides were also developed, which were termed as Gate All Around Field Effect Transistors (GAAFETs) [6][7][8][9]. But due to their complex and expensive fabrication processes, FinFETs remained the device of choice of the semiconductor industries.…”

Section: Introductionmentioning

confidence: 99%

Exploration of effects of gate underlap in HOI FinFETs at 10 nm gate length

Datta,

Nanda,

Sankar Dhar

2023

Phys. Scr.

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With sub-22 nm technology nodes, the short channel effects (SCEs) arose in FinFETs, which hindered the further scaling of devices. The leakage currents became detrimental with scaling of the gate oxide thickness below 2 nm, hence the demand for control of leakage currents due to corner effects in the sidewalls of FinFETs. Research suggested use of gate underlap (GUL) architectures to suppress the leakage currents. The objective of this paper is to utilize a GUL structure in a 10 nm gate length Heterostructure-On-Insulator (HOI) FinFET, encompassing a three layered strained channel architecture to enrich the drive currents. Different structures with GUL lengths of 1 nm, 3 nm and 5 nm are designed to study the electrical characteristics besides the effects of leakage currents and other SCEs. A noteworthy decrease is observed in the leakage currents with increasing GUL lengths. However, it also leads to decrease of drive currents of the devices. A trade-off between the enhanced dimensions of source/drain along with an optimized GUL length proves beneficial in the strained silicon channel devices. The 10 nm HOI device employing a 3 nm GUL with height/width of source/drain at 8 nm provides drive currents and leakage currents at par with the 10 nm HOI device with no underlap. But with higher Ion/Ioff current ratio and lower SCEs, this device with 3 nm underlap decreases corner effects and is observed from the electron velocity and total current density contours leading to faster switching speeds and optimized device performance towards semiconductor industry.

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“…9 To enhance the current level and bolster other performance parameters, various innovative device engineering techniques are being applied to FET device structures. [10][11][12][13][14][15] In order to address the challenges associated with short-channel effects (SCEs), merely scaling down gate lengths is insufficient. Consequently, alternative materials to silicon have been investigated to enhance nanowire based FET devices.…”

mentioning

confidence: 99%

Dielectrically-Modulated GANFET Biosensor for Label-Free Detection of DNA and Avian Influenza Virus: Proposal and Modeling

Yadav,

Das,

Rewari

2024

ECS J. Solid State Sci. Technol.

Self Cite

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This paper introduces a novel device called the gate all around engineered gallium nitride field effect transistor (GAAE-GANFET), designed specifically for label-free biosensing applications. This innovative gate-all-around engineering in GANFET integrates various device engineering techniques, such as channel engineering, gate engineering, and oxide engineering, to enhance biosensing performance. The channel engineering techniques refer to the use of a gallium nitride channel with a step-graded doping profile, divided into three distinct regions. In contrast, the gate engineering technique refers to the cylindrical split-gate-underlap architecture. The oxide engineering technique involves stacking Al2O3 and HfO2. Moreover, this biosensor incorporates two-sided gate underlap cavities that facilitate the immobilization of biomolecules. These open cavities not only provide structural stability but also simplify the fabrication process to a significant extent. The viability of this biosensor as a label-free biosensor has been evaluated using an antigen and an antibody from the Avian Influenza virus and DNA as the target biomolecules. The proposed analytical model and TCAD simulation results are in excellent agreement, demonstrating the reliability of the proposed device. Additionally, the biosensor's sensitivity, which depends on cavity length, doping concentration, gate metal work function, and temperature variation, has been thoroughly explored.

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Characterisation and Analysis of Schottky-Tube FET exhibiting Superior Characteristic Parameters

Cited by 5 publications

References 27 publications

Analytical analysis and linearity performance of dual metalhigh‐KSchottky nanowireFET(DM‐HK‐SNWFET)

Analytical analysis and linearity performance of dual metalhigh‐KSchottky nanowireFET(DM‐HK‐SNWFET)

Exploration of effects of gate underlap in HOI FinFETs at 10 nm gate length

Dielectrically-Modulated GANFET Biosensor for Label-Free Detection of DNA and Avian Influenza Virus: Proposal and Modeling

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