Abstract:This paper presents the results of the characterisation of a pixel sensor manufactured OKI 0.2 µm SOI technology integrated on a high-resistivity substrate, and featuring several pixel cell layouts for charge collection optimisation. The sensor is tested with short IR laser pulses, X-rays and 200 GeV pions. We report results on charge collection, particle detection efficiency and single point resolution.
“…Since the determination of the effective area used to derive the capacitance is affected by a large uncertainty, we use the C − V measurement only for establishing the voltage at which the sensor is fully depleted. From the evolution of the capacitance with the depletion voltage, we estimate that the detector is fully depleted for V d > 40 V. This is in agreement with what expected from the results of the 2010 beam test [2] and the resistivity deduced from the SRA analysis [6].…”
Section: Leakage Current and Depletion Thicknesssupporting
confidence: 89%
“…A grid of p-type guard-rings surrounds the I/O electronics at the chip periphery, while an external guard-ring surrounds the entire sensor design. This sensor has already been successfully tested with high momentum particles at the CERN SPS in 2010 [2]. The sensor under test is back-thinned using a commercial grinding technique [4] which has been already successfully employed for back-thinning CMOS Active Pixel Sensors [5].…”
Section: Thin Soi Sensor Experimental Setup and Data Analysismentioning
confidence: 99%
“…The thinned SOI chip has been placed upstream from a doublet made of the same SOI chips with full thickness. The doublet was already used in the 2010 beam test data taking [2]. The setup has been exposed to a 300 GeV π − beam.…”
Section: Thin Soi Sensor Experimental Setup and Data Analysismentioning
confidence: 99%
“…Silicon on Insulator (SOI) is one of the leading technologies for manufacturing these devices with the possibility of integrating advanced data processing capabilities. With the mitigation of the back-gating effect by implanting a buried p-well (BPW) beneath the buried oxide (BOX) [1], SOI pixel sensor prototypes have demonstrated high detection efficiency and micron-size single point resolution [2]. Because of the need to minimise multiple scattering in precision vertex tracking at future colliders, the total thickness of sensor ladders should be ≤ 100 µm of Si-equivalent while retaining high S/N and detection efficiency [3].…”
This paper presents the results of the characterisation of a thin fully depleted pixel sensor manufactured in SOI technology on high-resistivity substrate with high momentum charged particles. The sensor is thinned to and a thin phosphor layer contact is implanted on the back-plane. Its response is compared to that of thick sensors of same design in terms of signal and noise, detection efficiency and single point resolution based on data collected with 300 GeV pions at the CERN SPS. We observe that the charge collected and the signal-to-noise ratio scale according to the estimated thickness of the sensitive volume and the efficiency and single point resolution of the thinned chip are comparable to those measured for the thick sensors
“…Since the determination of the effective area used to derive the capacitance is affected by a large uncertainty, we use the C − V measurement only for establishing the voltage at which the sensor is fully depleted. From the evolution of the capacitance with the depletion voltage, we estimate that the detector is fully depleted for V d > 40 V. This is in agreement with what expected from the results of the 2010 beam test [2] and the resistivity deduced from the SRA analysis [6].…”
Section: Leakage Current and Depletion Thicknesssupporting
confidence: 89%
“…A grid of p-type guard-rings surrounds the I/O electronics at the chip periphery, while an external guard-ring surrounds the entire sensor design. This sensor has already been successfully tested with high momentum particles at the CERN SPS in 2010 [2]. The sensor under test is back-thinned using a commercial grinding technique [4] which has been already successfully employed for back-thinning CMOS Active Pixel Sensors [5].…”
Section: Thin Soi Sensor Experimental Setup and Data Analysismentioning
confidence: 99%
“…The thinned SOI chip has been placed upstream from a doublet made of the same SOI chips with full thickness. The doublet was already used in the 2010 beam test data taking [2]. The setup has been exposed to a 300 GeV π − beam.…”
Section: Thin Soi Sensor Experimental Setup and Data Analysismentioning
confidence: 99%
“…Silicon on Insulator (SOI) is one of the leading technologies for manufacturing these devices with the possibility of integrating advanced data processing capabilities. With the mitigation of the back-gating effect by implanting a buried p-well (BPW) beneath the buried oxide (BOX) [1], SOI pixel sensor prototypes have demonstrated high detection efficiency and micron-size single point resolution [2]. Because of the need to minimise multiple scattering in precision vertex tracking at future colliders, the total thickness of sensor ladders should be ≤ 100 µm of Si-equivalent while retaining high S/N and detection efficiency [3].…”
This paper presents the results of the characterisation of a thin fully depleted pixel sensor manufactured in SOI technology on high-resistivity substrate with high momentum charged particles. The sensor is thinned to and a thin phosphor layer contact is implanted on the back-plane. Its response is compared to that of thick sensors of same design in terms of signal and noise, detection efficiency and single point resolution based on data collected with 300 GeV pions at the CERN SPS. We observe that the charge collected and the signal-to-noise ratio scale according to the estimated thickness of the sensitive volume and the efficiency and single point resolution of the thinned chip are comparable to those measured for the thick sensors
“…One impressive development [22] demonstrated good performance in a particle beam [23]. Further work is planned to improve the radiation tolerance, lower due to accumulation of radiation induced charge in the buried oxide.…”
a b s t r a c tMonolithic pixel detectors integrating sensor matrix and readout in one piece of silicon are only now starting to make their way into high energy physics. Two major requirements are radiation tolerance and low power consumption. For the most extreme radiation levels, signal charge has to be collected by drift from a depletion layer onto a designated collection electrode without losing the signal charge elsewhere in the in-pixel circuit. Low power consumption requires an optimization of Q/C, the ratio of the collected signal charge over the input capacitance [1]. Some solutions to combine sufficient Q/C and collection by drift require exotic fabrication steps. More conventional solutions up to now require a simple in-pixel readout circuit. Both high voltage CMOS technologies and Monolithic Active Pixel Sensors (MAPS) technologies with high resistivity epitaxial layers offer high voltage diodes. The choice between the two is not fundamental but more a question of how much depletion can be reached and also of availability and cost. This paper tries to give an overview.
This paper presents the results of the characterisation of a back-illuminated pixel sensor manufactured in Silicon-On-Insulator technology on a high-resistivity substrate with soft X-rays. The sensor is thinned and a thin Phosphor layer contact is implanted on the back-plane. The response to X-rays from 2.12 up to 8.6 keV is evaluated with fluorescence radiation at the LBNL Advanced Light Source.
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