Characterisation of feasibility regions in FPGAs under adaptive DVFS

Dahir, Nizar; Campos, Pedro; Tempesti, Gianluca; Trefzer, Martin A.; Tyrrell, Andrew M.

doi:10.1109/fpl.2015.7293998

Cited by 2 publications

(1 citation statement)

References 10 publications

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“…The Intel Stratix 10 FPGA provides SmartVoltage ID control over VCC as its standard option that enables a smart voltage regulator to operate the device at lower VCC while maintaining performance [3]. Using these features, system level DVFS techniques are proposed for FPGAs [1,[4][5][6][7]. Hosseinabady et al [8] explain how to scale the voltage of the core logic in the Xilinx Zynq SoC.…”

Section: Preliminariesmentioning

confidence: 99%

Dynamic Energy Management of FPGA Accelerators in Embedded Systems

Hosseinabady

Nunez-Yanez

2018

ACM Trans. Embed. Comput. Syst.

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In this paper, we investigate how to utilise an FPGA in an embedded system to save energy. For this purpose, we study the energy efficiency of a hybrid FPGA-CPU device that can switch task execution between hardware and software with focus on periodic tasks. To increase the applicability of this task switching, we also consider the voltage and frequency scaling (VFS) applied to the FPGA to reduce the system energy consumption. We show that in some cases, if the task's period is higher than a specific level, the FPGA accelerator cannot reduce the energy consumption associated to the task and the software version is the most energy efficient option. We have applied the proposed techniques to a robot map creation algorithm as a case study which shows up to 38% energy reduction compared to the FPGA implementation. Overall, experimental results show up to 48% energy reduction by applying the proposed techniques at runtime on thirteen individual tasks.

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