Characteristic analysis of triple material tri-gate junctionless tunnel field effect transistor

Dewan, Monzurul Islam; Kashem, Md Tashfiq Bin; Subrina, Samia

doi:10.1109/icece.2016.7853924

Cited by 9 publications

(3 citation statements)

References 15 publications

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“…The channel potential gradually increases from source to drain, and it is assumed to present parabolic nature. The parabolic potential distribution can then be expressed as a second-order polynomial function 16 written as…”

Section: Surface Potential Modelingmentioning

confidence: 99%

“…The charge concentration per unit length per valley in the silicon inversion layer, considering silicon has four transverse and two longitudinal energy valleys, is given as 16) where N 1D is the 1-D density of states such that N 1D ¼ 1 ℏπ ffiffiffiffiffiffiffiffiffi ffi m x K p T and f (E) is the Fermi-Dirac distribution function. 23 The total inversion charge contributed by all the subbands can then be written as…”

Section: Quantum Inversion Charge Modelingmentioning

confidence: 99%

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Three‐dimensional analytical modeling and performance analysis of triple material trigate silicon‐on‐insulator MOSFET

Shora

Khanday

2019

Int J Numerical Modelling

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The semiconductor industry has implemented the technique of wrapping the gate electrode on different sides of channel to mitigate the degrading electrostatic effects in nanometer transistor. Intel adopted trigate architecture, wherein the channel is surrounded by gate electrode on three sides to improve the gate control over the channel. In order to further enhance the performance and diminish the short channel effects, triple material trigate silicon-oninsulator (SOI) MOSFET is explored in this work. An analytical model to determine the device electrostatics and match deviations due to device geometry has also been developed. The consequence of quantum confinement effects (QMEs), which arise due to ultra-thin body structure, on the inversion charge and threshold voltage has also been included. Thus, the analytical model presented in this work is based on a self-consistent solution of threedimensional Poisson's equation and two-dimensional Schrodinger equation with proper boundary conditions. The model is verified by the uniformity obtained between the results from analytical model and TCAD simulations. The superiority of the device has been demonstrated by comparing performance parameters like potential distribution, field variations, drain induced barrier lowering (DIBL) with already existing device structures like single material trigate (SMTG) and dual material trigate (DMTG) SOI MOSFETs

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Section: Surface Potential Modelingmentioning

confidence: 99%

Section: Quantum Inversion Charge Modelingmentioning

confidence: 99%

Three‐dimensional analytical modeling and performance analysis of triple material trigate silicon‐on‐insulator MOSFET

Shora

Khanday

2019

Int J Numerical Modelling

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“…The sub-threshold slop (SS) is the voltage applied on the gate to change the drain current by decade [13]. To obtaining a low sub-threshold slop (SS < 60mV /dec) and high switching performance (I ON /I OFF > 10 5 ) [14], the quantum mechanism in tunneling TFETs has been introduced as a substitution carrier injection mechanism in MOSFETs which suffers from thermal limitation [15][16][17].…”

Section: Introductionmentioning

confidence: 99%

Electrical characterization of si nanowire GAA-TFET based on dimensions downscaling

Abdul-kadir

Hashim²,

Shakib

et al. 2021

IJECE

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This research paper explains the effect of the dimensions of Gate-all-around Si nanowire tunneling field effect transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (VT). These parameters are critical factors of the characteristics of tunnel field effect transistors. The Silvaco TCAD has been used to study the electrical characteristics of Si-NW TFET. Output (gate voltage-drain current) characteristics with channel dimensions were simulated. Results show that 50nm long nanowires with 9nm-18nm diameter and 3nm oxide thickness tend to have the best nanowire tunnel field effect transistor (Si-NW TFET) characteristics.

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Trigate Junctionless Tunnel Field Effect Transistor

Gudelli,

Jayanthi,

Illuri

et al. 2024

Smart Grids as Cyber Physical Systems

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Characteristic analysis of triple material tri-gate junctionless tunnel field effect transistor

Cited by 9 publications

References 15 publications

Three‐dimensional analytical modeling and performance analysis of triple material trigate silicon‐on‐insulator MOSFET

Three‐dimensional analytical modeling and performance analysis of triple material trigate silicon‐on‐insulator MOSFET

Electrical characterization of si nanowire GAA-TFET based on dimensions downscaling

Trigate Junctionless Tunnel Field Effect Transistor

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