Characteristic diode parameters in thermally annealed Ni/p-InP contacts

Abstract

The Ni/p-InP Schottky diodes (SDs) have been prepared by DC magnetron sputtering deposition. After the diode fabrication, they have been thermally annealed at 700 °C for 1 min in N2 atmosphere. Then, the current–voltage characteristics of the annealed and non-annealed (as-deposited) SDs have been measured in the measurement temperature range of 60–400 K with steps of 20 K under dark conditions. After 700 °C annealing, an improvement in the ideality factor value has been observed from 60 to 200 K and the barrier height (BH) value approximately has remained unchanged in the measurement temperature range of 200–400 K. The BH of the annealed diode has decreased obeying the double-Gaussian distribution (GD) of the BHs with decreasing measurement temperature from 200 to 60 K. The BH for the as-deposited diode has decreased with decreasing temperature obeying the single-GD over the whole measurement temperature range. An effective Richardson constant value of 54.21 A/cm2K2 for the as-deposited SD has been obtained from the modified Richardson plot by the single-GD plot, which is in very close agreement with the value of 60 A/K2cm2 for p-type InP. The series resistance value of the annealed SD is lower than that of the non-annealed SD at each temperature and approximately has remained unchanged from 140 to 240 K. Thus, it can be said that an improvement in the diode parameters has been observed due to the thermal annealing at 700 °C for 1 min in N2 atmosphere.

Oncurrent-voltage and capacitance-voltage characteristics of metal-semiconductor contacts

“…It has been reported in Refs. [60,[192][193][194] that the variation of the diode parameters by thermal annealing may be attributed to changes of surface morphology and variation of nonstoichiometric defects at the interface vicinity and the formation of interfacial phases at the interface, and to the interfacial products that are formed at the interface.…”

Differential Depletion Charge Density of the Approximation of Schottky Diodes as Ohmic Annealed a Variety of Temperatures

“…In the fabrication process of making the diode, n-Si wafers, 450 µm in thicknesses and with ρ=1-10 Ω.cm resistivity and (100) orientation were used. The n-Si wafer was chemically cleaned of chemical and organic contaminants [1,2,7]. The n-Si wafer was then boiled for 3 min.…”

“…IF (nIV, nCh1), barrier height (IV, CV, Ch2), built-in potential (Vbi), donor concentration (ND), Fermi level (EF), interfacial thickness (Dit), interface state density (Nss) were calculated from the current-voltage (I-V) and capacitance-voltage (Cs-V) data [1][2][3][4][5][7][8][9][10][11][12][13][14]16]. The characteristics of the Schottky diode were calculated from ln(I)-V measurement and plotted depending on the voltage and the increasing ohmic temperatures.…”

“…In this article, Schottky parameters have been examined for both situations; forward bias and reverse bias. Ideality factor (IF) (nIV) [1,2], barrier height (ΦBH) [3,4], Cheung functions (Ch1, Ch2) [5,6], built-in potential (Vbi) [1,2], donor density (ND) [7], zero-voltage depletion length (W0 or L0), interfacial thickness (Dit) [6], interface state density (NSS) [8,9] and effective Fermi level (EF) are known as Schottky parameters [10]. A Schottky diode is comprised of four sections, namely ohmic junction, base structure, depletion layer and Schottky junction [10,11].…”

Electrical characteristics of Au/Ti/HfO2/n-GaAs metal-insulator-semiconductor structures with high-k interfacial layer

“…As seen in Table 1, the BH decreased with a decrease in the temperature because the current preferentially flows through the lowest BH with a decrease in temperature due to the BH inhomogeneity. [27][28][29][30][31][32][33][34][35] It can be seen from Figures 6 and 7 that the current value of the 5 nm MIS diode at a given bias is larger than that of the MIS diode of 3 nm up to the starting point of the downward curvature region of the I-V curve for all temperatures. The use of very thin interfacial layer increases the interfacial layer capacitance without generating excess gate current in a MOSFET and thus causes a large current through device.…”