2021
DOI: 10.1109/ted.2021.3059391
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Characteristics of InAs/GaSb Line-Tunneling FETs With Buried Drain Technique

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Cited by 12 publications
(5 citation statements)
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“…[1,4] The vertically stacked 2D/3D heterostructure is an important guarantee for the realization of the facetunneling mechanism, which greatly increases the effective tunneling area and enhances the gate control over the tunnel junction. [4][5][6] Therefore, the higher I ON and the steeper SS are obtained compared with the traditional point-tunneling mechanism. Consequently, steep subthreshold swing, large on-state current, and small off-state current can be obtained simultaneously in the 2D/3D TFETs.…”
Section: Introductionmentioning
confidence: 99%
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“…[1,4] The vertically stacked 2D/3D heterostructure is an important guarantee for the realization of the facetunneling mechanism, which greatly increases the effective tunneling area and enhances the gate control over the tunnel junction. [4][5][6] Therefore, the higher I ON and the steeper SS are obtained compared with the traditional point-tunneling mechanism. Consequently, steep subthreshold swing, large on-state current, and small off-state current can be obtained simultaneously in the 2D/3D TFETs.…”
Section: Introductionmentioning
confidence: 99%
“…[2,4] Meanwhile, the pristine interface of the 2D/3D heterostructure due to the dangling-bond-free interface of the 2D material significantly suppresses the trap-assisted tunneling process (TAT) induced by interface traps, which is a Gordian knot of III-V heterojunction TFETs and leads to the relatively high off-state current (I OFF ) and subthreshold swing (SS). [5,6] Moreover, the atomically thin channel enhances the electrostatic control over the entire tunneling junction for ultrasteep subthreshold switching. [4] Due to the existence of the van der Waals gap at the interface, the ultrasharp doping profile is available for the 2D/3D tunnel heterostructure, which improves the tunneling efficiency and increases the on-state current (I ON ).…”
Section: Introductionmentioning
confidence: 99%
“…Consequently, this presents a significant obstacle to further advancement in information density and circuit performance. Although steep slope devices, such as negative-capacitance FETs (NCFETs) [5][6][7][8][9] and tunneling FETs (TFETs) [10][11][12][13][14], can mitigate this issue, the number of bits is inherently smaller than the number of gates in a binary Boolean logic system [2].…”
Section: Introductionmentioning
confidence: 99%
“…The conventional TFET faces three challenges: (1) TAT effect; (2) high thermal budget; and (3) low ON-state current. To overcome these limitations, various solutions have been proposed in many papers, such as heavily doped Gaussian drain regions [ 9 ], multiple gates [ 10 – 13 ], pocket structures [ 14 ], heterostructures formed using small bandgap materials [ 15 19 ], the high electron mobility characteristics of III–V materials [ 20 , 21 ], ferroelectric material NC-TFET [ 22 ], or more novel two-dimensional materials [ 23 , 24 ].…”
Section: Introductionmentioning
confidence: 99%