Characteristics of narrow-channel polysilicon thin-film transistors

Yamauchi, Noriyoshi; Hajjar, Jean-Jacques; Reif, R.; Nakazawa, K.; Tanaka, Keiji

doi:10.1109/16.119042

Cited by 20 publications

(26 citation statements)

References 7 publications

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“…So, at low drain bias, the subthreshold swing is continuously improved as channel width decreases. When V ds increases, the swing is decreased owing to the floating body effect [3,13]. For TFTs hydrogenated for 8 h, the channel can sustain lots of unbonded (highly mobile) hydrogen atoms which will collide with carriers [14].…”

Section: Resultsmentioning

confidence: 99%

“…As the TFTs are further scaled to meet the requirement of higher circuit density, the subthreshold characteristics of the TFTs become critical for these applications, thus requiring more study. Recently, the threshold voltage, channel mobility, subthreshold swing, leakage current and on:off ratio have been characterized and widely studied [3][4][5]. However, the control of punchthrough is another problem, which becomes more serious as the channel length shrinks into the submicron region.…”

Section: Introductionmentioning

confidence: 99%

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Selection of the resonator type

Anan'ev¹

1989

Sov. J. Quantum Electron.

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The punchthrough phenomena of submicron polysilicon thin-film transistors (TFTs) with and without hydrogenation have been investigated in detail. Unhydrogenated TFT shows better punchthrough immunity. At high drain bias, the subthreshold swing of unhydrogenated TFTs is much smaller than that of hydrogenated TFTs. This is contrary to the phenomenon of TFTs operated under normal operated voltage (|V ds | < 8 V). Furthermore, as the channel width of unhydrogenated TFTs becomes comparable with or smaller than the polysilicon grain size, the subthreshold swing at low drain bias is continuously improved with decreasing channel width. The trend of subthreshold swing is in the opposite direction for drain biases above 8 V. A model, which takes the effect of charged traps into account, is proposed to interpret the punchthrough phenomena of TFTs.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Selection of the resonator type

Anan'ev¹

1989

Sov. J. Quantum Electron.

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“…nition of threshold voltage at the critical condition y d = L g /2 is identical to that at the maximum of barrier height. However, we have not taken into account the short-channel effect [22], narrow-channel effect [23], and the Drain Induced Barrier Lowering (DIBL) effect [24] on the threshold voltage of poly-Si TFTs. Therefore, further study on the threshold voltage of poly-Si TFTs should be needed.…”

Section: Discussionmentioning

confidence: 99%

A new analytical threshold voltage model for the doped polysilicon thin-film transistors

Yao

Zheng

2009

Solid-State Electronics

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“…1(a) dimension, the hydrogenation passivation and the formation process of gate oxide. Additionally, it has been reported, some defects along channel edge will be induced during poly channel etching [4]. Before hydrogenation, the traps in grain boundaries are dominant, therefore, as the channel width is reduced to sub-grain size ( 0.6 m) region, the traps in the grain boundaries are drastically decreased due to the disappearance of grain boundaries in the channel region.…”

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confidence: 99%

“…Especially as the channel dimension of the poly-Si TFT is shorten to or small than the grain size of the poly-Si TFT's. In past, many narrow width effects on these top-gate TFT's of sub-grain size with thermal gate oxide have been reported [3]-[5] and found that the threshold voltage is indeed decreased drastically for both hydrogenated and unhydrogenated samples [4]. Hence, it is worthy to investigate the narrow width effects on bottom-gate poly-Si TFT's, since they are currently used for high density TFT-SRAM and have different technologies for gate oxide.…”

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confidence: 99%

Narrow width effects of bottom-gate polysilicon thin film transistors

Yaung

Fang

Hwang

et al. 1998

IEEE Electron Device Lett.

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The effects of channel width on the characteristics of both hydrogenated and unhydrogenated bottom-gate polysilicon thin-film transistors (TFT's) were investigated in detailed. For unhydrogenated and silane gas formed TFT's, a drastic decrease in threshold voltage is observed due to the grain-boundary traps are reduced when the channel width is reduced to less than grain size, but the minimum drain current sensitive to intragranular tail states are nearly unchanged. After hydrogenation, almost grain boundary traps and intragranular tail states were passivated, the effect of traps along poly channel edges caused by the definition of poly channel pattern will dominate i.e., threshold voltage and minimum drain current increase with decreasing channel width. Also disilane gas formed TFT's are studied for comparison. P OLY-Si thin-film transistors (TFT's) grown by LPCVD are currently used for liquid crystal display and high density SRAM [1], [2]. It is well known that the performances of these applications are limited by the trap states at grain boundaries in the poly-Si TFT's. As the TFT's are further miniaturized to meet the requirement of higher circuit density, the limitation of trap states will be more severe. Especially as the channel dimension of the poly-Si TFT is shorten to or small than the grain size of the poly-Si TFT's. In past, many narrow width effects on these top-gate TFT's of sub-grain size with thermal gate oxide have been reported [3]-[5] and found that the threshold voltage is indeed decreased drastically for both hydrogenated and unhydrogenated samples [4]. Hence, it is worthy to investigate the narrow width effects on bottom-gate poly-Si TFT's, since they are currently used for high density TFT-SRAM and have different technologies for gate oxide. In this letter, the narrow width effects on bottom-gate TFT's of sub-grain size with and without hydrogen-plasma treatment are investigated and reported in detail.In the samples, n polysilicon films were deposited by LPCVD at 620 C to a thickness of 55 nm on a 200 mm Si wafer pre-coated with 400-nm-thick thermal oxide. After gate definition, a 30-nm gate oxide was deposited by LPCVD at 780 C. Next, a 30-nm amorphous silicon was deposited by thermal decomposition of silane or disilane. Then, the channel Manuscript are with the Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan, R.O.C.Publisher Item Identifier S 0741-3106(98)08174-9.was implanted with phosphorous at a dose of 5 10 cm and recrystallized at 600 C in N ambient for 24 h. Source and drain regions are implanted with boron at a dose of 5 10 cm . A BPTEOS layer was deposited and planarized at 850 C for 30 minutes to eliminate the topography caused by buried polysilicon. Finally, Al-Cu alloy was deposited and patterned. The channel width of TFT's range from 2 m to 0.35 m. The channel length of all samples was defined at 0.45 m to exclude the variation effect of channel length. There are 400 TFT's connected in parallel; therefore the deviation caused by measurement system can be minimized....

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Characteristics of narrow-channel polysilicon thin-film transistors

Cited by 20 publications

References 7 publications

Selection of the resonator type

Selection of the resonator type

A new analytical threshold voltage model for the doped polysilicon thin-film transistors

Narrow width effects of bottom-gate polysilicon thin film transistors

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