Narrow width effects of bottom-gate polysilicon thin film transistors

Abstract

The effects of channel width on the characteristics of both hydrogenated and unhydrogenated bottom-gate polysilicon thin-film transistors (TFT's) were investigated in detailed. For unhydrogenated and silane gas formed TFT's, a drastic decrease in threshold voltage is observed due to the grain-boundary traps are reduced when the channel width is reduced to less than grain size, but the minimum drain current sensitive to intragranular tail states are nearly unchanged. After hydrogenation, almost grain boundary traps and intragranular tail states were passivated, the effect of traps along poly channel edges caused by the definition of poly channel pattern will dominate i.e., threshold voltage and minimum drain current increase with decreasing channel width. Also disilane gas formed TFT's are studied for comparison. P OLY-Si thin-film transistors (TFT's) grown by LPCVD are currently used for liquid crystal display and high density SRAM [1], [2]. It is well known that the performances of these applications are limited by the trap states at grain boundaries in the poly-Si TFT's. As the TFT's are further miniaturized to meet the requirement of higher circuit density, the limitation of trap states will be more severe. Especially as the channel dimension of the poly-Si TFT is shorten to or small than the grain size of the poly-Si TFT's. In past, many narrow width effects on these top-gate TFT's of sub-grain size with thermal gate oxide have been reported [3]-[5] and found that the threshold voltage is indeed decreased drastically for both hydrogenated and unhydrogenated samples [4]. Hence, it is worthy to investigate the narrow width effects on bottom-gate poly-Si TFT's, since they are currently used for high density TFT-SRAM and have different technologies for gate oxide. In this letter, the narrow width effects on bottom-gate TFT's of sub-grain size with and without hydrogen-plasma treatment are investigated and reported in detail.In the samples, n polysilicon films were deposited by LPCVD at 620 C to a thickness of 55 nm on a 200 mm Si wafer pre-coated with 400-nm-thick thermal oxide. After gate definition, a 30-nm gate oxide was deposited by LPCVD at 780 C. Next, a 30-nm amorphous silicon was deposited by thermal decomposition of silane or disilane. Then, the channel Manuscript are with the Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan, R.O.C.Publisher Item Identifier S 0741-3106(98)08174-9.was implanted with phosphorous at a dose of 5 10 cm and recrystallized at 600 C in N ambient for 24 h. Source and drain regions are implanted with boron at a dose of 5 10 cm . A BPTEOS layer was deposited and planarized at 850 C for 30 minutes to eliminate the topography caused by buried polysilicon. Finally, Al-Cu alloy was deposited and patterned. The channel width of TFT's range from 2 m to 0.35 m. The channel length of all samples was defined at 0.45 m to exclude the variation effect of channel length. There are 400 TFT's connected in parallel; therefore the deviation caused by measurement system can be minimized....

Mechanism of device instability for unhydrogenated polysilicon TFTs under off-state stress

“…At high V ds the high-field tunnelling mechanism becomes dominant, causing device leakage to depend on the number of traps within the TFT [6]. As the channel dimension is equal to or smaller than grain size, a large-dimensional TFT has more traps [7], thus showing the tunnelling phenomenon at lower V ds (∼−10 V). We have proposed a model to explain this post-stressed swing variation of unhydrogenated TFTs as follows: the schematic energy diagram of the TFTs under off-state stress is shown at the bottom of figure 1.…”

SPICE simulation of nanoscale non-crystalline silicon TFTs in spiking neuron circuits

“…In many other electronic devices, short channel [26] and narrow width effects [27][28][29] become important in this range. To test the validity of the assumption, a-Si:H transistors with Ti Schottky barrier source/drain contacts and Effective Channel Width W eff (μm) a common back gate have been fabricated and characterized.…”

Technology, performance and degradation characteristics of SLS ELA thin film transistors

“…However, all of the TFTs studied were in small-grain polysilicon with significantly larger trap densities. Only Yaung et al [19] reported a V th increase with decreasing channel width for hydrogenated polysilicon TFTs, where the trap density is reduced.…”