Mechanism of device instability for unhydrogenated polysilicon TFTs under off-state stress

Abstract

The effects of off-state stress (V gs = 0 V, V ds = 0 to −20 V) on unhydrogenated p-channel polysilicon thin-film transistors (TFTs) were studied. It was observed that the post-stressed subthreshold swing is first improved due to the annealing effect from the interaction of tunnelling electrons and captured holes. As the stress time increases or as the stress bias increases, the generation of traps caused by tunnelling electrons will cancel out the annealing effect and then degrade the subthreshold swing. In addition, the trapping of tunnelling electrons in the gate oxide causes a shift of threshold voltage. However, improving the quality of the gate oxide interface by oxidation of the channel polysilicon on submicrometre bottom-gate TFTs can reduce the impact of the off-state stress.

Effects of Electrical Bias Stress on the Performance of ZnO-Based TFTs Fabricated by RF Magnetron Sputtering

“…This indicates that when a negative gate bias was applied to the TFT devices, trapped charge carriers were re-emitted out of the insulator layer and the threshold voltage was recovered. 16 An upward shift ͑about 3 dec͒ in Fig. 6 clearly shows the leakage current increases with bias stress, indicating that the trapped charges cause the major failure of the ZnO TFTs.…”

“…Tremendous research efforts have been exerted to study the effect of electrical stress on device performance in the case of conventional a-Si:H TFTs. [13][14][15][16][17] The performance of poststressed ZnO TFTs is similar to that of a-Si:H TFTs. Nevertheless, some significant differences are observed in the poststressed transfer characteristics of ZnO TFTs.…”

Electrical stressing effects in solid-phase crystallized polysilicon thin film transistors

“…The subsequent positive V th degradation has an approximately logarithmic time dependence; this behaviour indicates a charge trapping process occurring in the oxide or at the interface [21]. During V GS stressing, the energetic electrons are injected into the oxide, creating interface states and weak oxide areas susceptible to electron trapping [18,22]. Local field enhancement, due to asperities present because of the polycrystalline structure of the channel in the TFTs, is instrumental in effecting the injection and trapping of channel electrons; the polysilicon grain size is significantly smaller than the channel length of these devices and thus grain boundaries and asperities exist within the channel.…”

“…Although hydrogen passivates grain boundary defects, not all of its effects are beneficial: it is considered responsible for light-induced metastability in amorphous silicon [15], it is thought to create instabilities in thermal SiO 2 and at the oxide/silicon interface [16] and it has been reported to be released due to hot carrier stress resulting in degradation of bipolar transistors [17]. Thus, interest for research in unhydrogenated devices has significantly increased recently [18,19]. In this study, parameter extraction is performed using measurements before electrical stressing and after specific durations of stress application for various stressing conditions.…”