Electrical stressing effects in solid-phase crystallized polysilicon thin film transistors

Abstract

The evolution of the electrical parameters of solid-phase crystallized polysilicon thin film transistors under various stressing-gate and drain-bias values was studied. Under V GS stressing, the threshold voltage V th exhibits an initial negative shift attributed to hole trapping and a subsequent turnaround, occurring sooner for larger stressing V GS , towards positive shifts with a logarithmic time dependence, indicating an electron trapping process occurring in the oxide and at the polysilicon/SiO 2 interface. The subthreshold swing, the midgap trap state density and the transconductance exhibit a concomitant logarithmic degradation, attributed to a stress-induced acceptor trap creation at the interface and in the polysilicon active layer, corroborating the electron trapping process inferred from the V th data. The simultaneous application of a small V DS stressing in combination with the V GS stressing suppresses this V th turnaround effect and enhances the degradation of all parameters. The reduction of the turnaround stressing time as well as the increase in the subthreshold swing and the midgap trap state density correlated with the increase of the stressing current I DS , indicating a concomitant increase of the stress-induced trap creation and the electron trapping.

Effects of hot carriers in offset gated polysilicon thin-film transistors

“…For such applications, one of the major problems of the polysilicon TFTs is their instability induced by hot-carrier effects. In previous work, it has been pointed out that the instability of polysilicon TFTs is more serious than that of single-crystalline silicon MOSFETs after electrical stress [3][4][5]. The lower stability of polysilicon TFTs is associated with the high density of in-grain and grain boundary defects which enhance the local electric field near the drain region and with the poor polysilicon/oxide interface quality [6].…”