On-state and off-state stress-induced degradation in unhydrogenated solid phase crystallized polysilicon thin film transistors

Kouvatsos, Dimitrios N.

doi:10.1016/s0026-2714(02)00120-8

Cited by 6 publications

(2 citation statements)

References 27 publications

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“…9,10 The generation electrons injected into gate oxide layer, which can be referred to lucky current model, to form oxide trapped charges and interface states. 11 Otherwise, the generation holes reflowed to source terminal causing grain boundary states. The path of hole reflowing is described in Fig.…”

Section: Gate-to-drain Capacitance Verifying the Continuous-wave Greementioning

confidence: 99%

Gate-to-drain capacitance verifying the continuous-wave green laser crystallization n-TFT trapped charges distribution under dc voltage stress

Hsieh

Wang

Chen

et al. 2009

Applied Physics Letters

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In this work, a metrology was proposed to realize the distribution of fixed oxide trapped charges and grain boundary trapped states. The (continuous-wave green laser crystallization) n-channel thin-film transistors (TFTs) were forced by dc voltage stress, VG=VD. The gate-to-drain capacitance, CGD−VG, with varying frequency of applied small signal was developed. To probe the distribution of these defects, the difference (initial capacitance values minus stressed capacitance values) of CGD−VG with different frequencies was precisely studied.

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Section: Gate-to-drain Capacitance Verifying the Continuous-wave Greementioning

confidence: 99%

Gate-to-drain capacitance verifying the continuous-wave green laser crystallization n-TFT trapped charges distribution under dc voltage stress

Hsieh

Wang

Chen

et al. 2009

Applied Physics Letters

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“…8,9) The poor stability of poly-Si TFTs under electrical stress is due to the high density of in-grain and grain boundary defects. [10][11][12][13][14][15][16][17][18][19][20][21] Most previous works related to the stability of poly-Si TFTs have been mainly focused on long-channel devices. [22][23][24] The degradation phenomenon of short-channel poly-Si TFTs caused by the low gate and high drain voltages is mainly originated by hot-carrier stress.…”

Section: Introductionmentioning

confidence: 99%

Hot-Carrier Effects in Short Channel (L = 1.5 µm) p-Type Polycrystalline Silicon Thin-Film Transistors

Choi¹,

Kim

et al. 2012

Jpn. J. Appl. Phys.

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We have investigated the reliability of short-channel (L = 1.5 µm) p-type excimer-laser-annealed (ELA) polycrystalline silicon (poly-Si) TFTs under hot-carrier related static bias stress. The threshold voltage (ΔV TH = 0.59 V) of short-channel TFTs (L = 1.5 µm) was significantly more shifted to the positive direction than that (ΔV TH = 0.02 V) of long-channel TFTs (L = 7 µm) under the same stress condition for 100 s. This positive shift of threshold voltage may be attributed to electron trapping at the interface between the poly-Si film and the gate oxide layer. In addition, we have extracted the length of the drain extension from an equation of the pseudo-lightly doped drain (LDD) model to verify the existence of free hole charges induced near the drain junction. The transfer characteristics of the normal and drain-source swapped modes as well as the capacitance–voltage (C–V) characteristics with variation in channel length after the bias stress indicate that the electron trapping at the gate insulator/channel interface mainly occurred near the drain junction region. Furthermore, the threshold voltage of the short-channel ELA poly-Si TFTs with L = 1.5 µm was largely increased as the stress temperature was increased from room temperature to 100 °C, which indicates that the impact ionization occurs more at higher temperature.

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Drain voltage sweeping-induced degradation in n-type low-temperature polysilicon thin film transistors

Zhou

Wang

Hao

et al. 2010

Semicond. Sci. Technol.

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Device degradation under the drain voltage (V d ) sweeping, where V d lineally sweeps at a fixed gate voltage, has been investigated for n-type low-temperature (LT) polysilicon thin film transistors (TFTs). The degradation mechanism is found to be related to the dc hot carrier (HC) effect even for a sweeping time as short as ∼μs. Since a routine device output measurement can induce significant (as large as 30%) on-current (I on ) degradation in such LT crystallized TFTs, only by using the optimized pulse IV method can one obtain an accurate output measurement without much affecting the device under test (e.g., <0.5% of I on degradation).

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On-state and off-state stress-induced degradation in unhydrogenated solid phase crystallized polysilicon thin film transistors

Cited by 6 publications

References 27 publications

Gate-to-drain capacitance verifying the continuous-wave green laser crystallization n-TFT trapped charges distribution under dc voltage stress

Gate-to-drain capacitance verifying the continuous-wave green laser crystallization n-TFT trapped charges distribution under dc voltage stress

Hot-Carrier Effects in Short Channel (L = 1.5 µm) p-Type Polycrystalline Silicon Thin-Film Transistors

Drain voltage sweeping-induced degradation in n-type low-temperature polysilicon thin film transistors

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