One of the most critical issues for Ge/III-V MOSFETs, which have been regarded as a promising CMOS structure under sub 10 nm regime, is gate insulator formation satisfying the requirements of MOS interface quality and thin equivalent oxide thickness (EOT). In this paper, we focus on viable gate stack technologies realizing these requirements. As for Ge gate stacks, we present a ultrathin EOT Al 2 O 3 /GeO x /Ge gate stack fabricated by a plasma post oxidation method and pMOSFETs using this gate stack. The GeO x /Ge MOS interface properties are systemically examined, and the relations of the interface state density (D it ) with the GeO x thickness and the chemical conditions are studied. (100) Ge pMOSFETs using this gate stack is demonstrated with EOT down to 0.98 nm and high hole peak mobility of 401 cm 2 /Vs. As for InGaAs gate stacks, we show the impact of Al 2 O 3 inter-layers on interface properties of HfO 2 /InGaAs MOS interfaces. It is found that the insertion of 0.2-nm-thick ultrathin Al 2 O 3 inter-layer can effectively improve the HfO 2 /InGaAs interface properties such as the frequency dispersion and the stretch-out of C-V characteristics and D it . The 1-nm-thick capacitance equivalent thickness (CET) in the HfO 2 /Al 2 O 3 /InGaAs MOS capacitors is realized with good interface properties and low gate leakage of 2.4×10 -2 A/cm 2 .