Characteristics of the transient wafer temperature distribution in a furnace for semiconductor fabrication processes

Abstract

In the high‐temperature process of semiconductors, the temperature distribution on the wafer surface during the procedures of the wafer insertion into and removal from the oxidation or diffusion furnace is important in determining the density of the dislocation due to the thermal stress and the uniformities of both the oxide thickness and the diffusion depth. As the size of a wafer and the density of integration increase, the analysis of the thermal transient characteristics becomes more important. This paper analyzes the model of the temperature transient characteristics proposed previously and describes the transient characteristics on a wafer by measuring the temperature distribution en a wafer in a furnace using an infrared radiometer. The simulation for a case where a wafer of 150 mm in diameter is inserted into a furnace at a speed of 20 cm/min indicates that the temperature variation on a wafer at every moment is as high as 150°C. This result agrees with the experimental result within an accuracy of 25°C. When the insertion speed is 100 cm/min, the temperature variation increases by 20 to 30 percent and is maintained until the wafer reaches the high‐temperature zone. This is caused by the increase in the rate of temperature change with time due to the radiation from the tube wall which is the external heat source. This tendency is more noticeable for waters located at the middle row.

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“…Mokuya et al investigated the temperature distributions in regularly spaced wafers in a row in a furnace tube theoretically and experimentally, and showed that the temperature gradient in a wafer becomes larger from the bottom position (Y ϭ 0) to the top position and the distribution was different according to the wafer set position on the boat. [34][35][36] This indicates that the thermal stress which is nearly proportional to the temperature gradient 37 becomes higher near the top position of wafer, i.e., near the orientation flat in the present work. The stress induced in the Si substrate enhances the generation of point defects (interstitial and vacancy).…”