Characterization and analysis of vertical coupling impact on receiver performance in high speed serial interface

Shim, Yujeong; Oh, Dan; Sun, Shishuang; Zhang, Jianmin; Jiang, Jenny Xiaohong; Nguyen, Cong Tien; Chandrasekhar, J.; Tretiakov, Yuri

doi:10.1109/epeps.2013.6703504

Cited by 2 publications

(1 citation statement)

References 2 publications

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“…Therefore, placement of pads and vias in PCB also depends on package ball pin-out assignment. Even though the length of PCB via is typically shorter than horizontal interconnections such as PCB trace, the coupling impact is not negligible due to the difficulty of control [7]. Unlike reducing the coupling of horizontal interconnections, there are not many techniques to reduce crosstalk between PCB vias.…”

Section: Introductionmentioning

confidence: 99%

Design of package BGA pin-out for >25Gb/s high speed SerDes considering PCB via crosstalk

Yao

Lim

et al. 2015

2015 IEEE Symposium on Electromagnetic Compatibility and Signal Integrity

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Fast growing bandwidth demands for networking and data center applications continuously face difficult signal integrity challenges. Among them, serializer/deserializer (SerDes) package pin-out and its corresponding printed circuit board (PCB) via crosstalk have become a significant source of high jitter and limit the performance of high speed serial links. In this paper, a variety of far-end crosstalk (FEXT) and nearend crosstalk (NEXT) SerDes pin-out patterns are designed and investigated to explore the crosstalk performance for interfaces running 25Gb/s and beyond. The impact of PCB routing layer selection and via stub are also considered. Both frequency domain and time domain analysis are studied based on 3-dimensional (3D) full wave electromagnetic (EM) simulation, and the results are compared along with the calculated integrated crosstalk noise (ICN) to find the pattern with better signal isolation. A PCB test vehicle is designed and manufactured to provide measurement and verification results by using broadband micro-probes and multi-port vector network analyzer (VNA). The optimized pinout is then selected to evaluate the overall link performance based on the input/output buffer information specification algorithmic modeling interface (IBIS-AMI) model from silicon vendors.

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Section: Introductionmentioning

confidence: 99%

Design of package BGA pin-out for >25Gb/s high speed SerDes considering PCB via crosstalk

Yao

Lim

et al. 2015

2015 IEEE Symposium on Electromagnetic Compatibility and Signal Integrity

View full text Add to dashboard Cite

show abstract

Improved PCB via pattern to reduce crosstalk at package BGA region for high speed serial interface

Shim

2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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Characterization and analysis of vertical coupling impact on receiver performance in high speed serial interface

Cited by 2 publications

References 2 publications

Design of package BGA pin-out for >25Gb/s high speed SerDes considering PCB via crosstalk

Design of package BGA pin-out for >25Gb/s high speed SerDes considering PCB via crosstalk

Improved PCB via pattern to reduce crosstalk at package BGA region for high speed serial interface

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Characterization and analysis of vertical coupling impact on receiver performance in high speed serial interface

Cited by 2 publications

References 2 publications

Design of package BGA pin-out for &#x003E;25Gb/s high speed SerDes considering PCB via crosstalk

Design of package BGA pin-out for &#x003E;25Gb/s high speed SerDes considering PCB via crosstalk

Improved PCB via pattern to reduce crosstalk at package BGA region for high speed serial interface

Contact Info

Product

Resources

About

Design of package BGA pin-out for >25Gb/s high speed SerDes considering PCB via crosstalk

Design of package BGA pin-out for >25Gb/s high speed SerDes considering PCB via crosstalk