Characterization and bottleneck analysis of a 64-bit ARMv8 platform

Laurenzano, Michael A.; Tiwari, Ananta; Cauble-Chantrenne, Allyson; Jundt, Adam; Ward, William A.; Campbell, Roy L.; Carrington, Laura

doi:10.1109/ispass.2016.7482072

Cited by 17 publications

(17 citation statements)

References 29 publications

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“…Second, our performance-per-watt results show that emerging ARM-based platforms generally show much lower energy efficiency than the KNL and mainstream Intel platforms. This finding opposes the conclusions of previous studies [2], [4] that report or estimate high energy-efficiency of the ARM platforms (reasons for this are discussed in detail in Section IV).…”

Section: Introductioncontrasting

confidence: 99%

“…The HPC system software for emerging platforms is still under development; for example, the first math libraries for ARM-based servers were released two years ago [21]. Similar studies confirm that system software stack on emerging platforms is relatively immature, which limits the achievable performance [4], [22], [23]. Finally, ThunderX shows very low FLOPS and memory utilization of 23% and 27%, respectively.…”

Section: E Theoretical Vs Sustained Flops/s and Memory Bandwidthmentioning

confidence: 95%

“…Laurenzano et al [4] compare the performance, power and energy consumption, and bottlenecks of Sandy Bridge, Atom, Haswell and X-Gene 1 servers. This analysis is based on system measurements with a large number of benchmarks and statistical modeling.…”

Section: Related Workmentioning

confidence: 99%

“…We strongly advocate that any comparison between the platforms should start with the performance and energy-efficiency of HPL and HPCG as the boundaries of the compute-intensive and memory-intensive HPC applications. However, most of the previous studies [2]- [4] that compare emerging and mainstream HPC platforms do not include these results.…”

Section: Introductionmentioning

confidence: 99%

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Mainstream vs. Emerging HPC: Metrics, Trade-Offs and Lessons Learned

Radulovic

Asifuzzaman

Zivanovic

et al. 2018

2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

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Various servers with different characteristics and architectures are hitting the market, and their evaluation and comparison in terms of HPC features is complex and multidimensional. In this paper, we share our experience of evaluating a diverse set of HPC systems, consisting of three mainstream and five emerging architectures. We evaluate the performance and power efficiency using prominent HPC benchmarks, High-Performance Linpack (HPL) and High Performance Conjugate Gradients (HPCG), and expand our analysis using publicly available specialized kernel benchmarks, targeting specific system components. In addition to a large body of quantitative results, we emphasize six usually overlooked aspects of the HPC platforms evaluation, and share our conclusions and lessons learned. Overall, we believe that this paper will improve the evaluation and comparison of HPC platforms, making a first step towards a more reliable and uniform methodology. Index Terms-HPC, emerging and mainstream architectures, energy efficiency, weak vs. strong cores, memory latency and bandwidth, Byte/FLOP ratio

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Section: Introductioncontrasting

confidence: 99%

Section: E Theoretical Vs Sustained Flops/s and Memory Bandwidthmentioning

confidence: 95%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Mainstream vs. Emerging HPC: Metrics, Trade-Offs and Lessons Learned

Radulovic

Asifuzzaman

Zivanovic

et al. 2018

2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

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“…While there is an extensive body of work on optimizing SpMV on SMP and multi-core architectures [23,25], there is little work on investigating SpMV performance on the ARMv8-based many-core architectures. Given that the ARMv8-based processor IP is emerging as an alternative for HPC processor architecture [18,36,50], it is crucial to understand how well different sparse matrix storage formats perform on such architectures and what affects the resulting performance. Understanding this can not only help software developers to write better code for the next-generation HPC systems, but also provide useful insights for hardware architects to design more efficient hardware for this important application domain.…”

Section: Introductionmentioning

confidence: 99%

Optimizing Sparse Matrix–Vector Multiplications on an ARMv8-based Many-Core Architecture

Chen

Fang

Chen

et al. 2019

Int J Parallel Prog

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Sparse matrix-vector multiplications (SpMV) are common in scientific and HPC applications but are hard to be optimized. While the ARMv8based processor IP is emerging as an alternative to the traditional x64 HPC processor design, there is little study on SpMV performance on such new many-cores. To design efficient HPC software and hardware, we need to understand how well SpMV performs. This work develops a quantitative approach to characterize SpMV performance on a recent ARMv8-based many-core architecture, Phytium FT-2000 Plus (FTP). We perform extensive experiments involved over 9,500 distinct profiling runs on 956 sparse datasets and five mainstream sparse matrix storage formats, and compare FTP against the Intel Knights Landing many-core. We experimentally show that picking the optimal sparse matrix storage format and parameters is non-trivial as the correct decision requires expert knowledge of the input matrix and the hardware. We address the problem by proposing a machine learning based model that predicts the best storage format and parameters using input matrix features. The model automatically specializes to the many-core architectures we considered. The experimental results show that our approach achieves on average 93% of the best-available performance without incurring runtime profiling overhead.

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