Characterization and modeling of fast traps in thermal agglomerating germanium nanocrystal metal-oxide-semiconductor capacitor

Abstract

In this paper, the germanium ͑Ge͒ nanocrystals ͑NCs͒ are synthesized by using the rapid-thermal annealing and are embedded into a three-layer ͑SiO 2 / NCs-Ge/ SiO 2 ͒ capacitor structure. The samples with/without the postmetallization annealing ͑PMA͒ treatment are investigated to compare and study the PMA affections. The charge storage characteristics of our samples are investigated with the capacitance-voltage ͑C-V͒ hystereses. The frequency independence of hysteresis windows is found and attributed to NCs as slow traps with a large characteristic time constant. The frequency-dependent C-V and conductance-voltage ͑G-V͒ experiments are further introduced to study the interface traps and the fast traps induced by the NC formation. In order to extract the related trap characteristics from the measured C-V and G-V, we propose to utilize the equivalent circuit and single-level trap model based on Shakley-Read-Hall theory. Three associated parameters including the areal trap density, trap conductance, and semiconductor capacitances are used to confirm that the single-level trap model is truly appropriate for our samples. It is then found from the model that the areal trap density is high and approaches almost uniform distribution along the valence band and bandgap but significantly reduced and then becomes decreased from valence band to the midgap after PMA treatment. In addition, after PMA treatment, the characteristic time constant becomes smaller for one order of magnitude at the same gate bias. It is attributed to the reduction of trap density and also agrees that the interface traps are dominant and has a small characteristic time constant.

Hf-based high-k materials for Si nanocrystal floating gate memories

“…From the inset of Figure 3b , it is noteworthy that the same amount of hysteresis and stored charge was obtained irrespective of the measurement frequency. Hence, the capacitance shift can be attributed to the presence of fast traps and/or border traps (near-interfacial traps), which can have a rapid communication with the underlying Si substrate [ 24 ]. From all these observations, we can ascertain that the observed memory window is predominantly due to the formation of Si-ncs.…”

Different charging behaviors between electrons and holes in Si nanocrystals embedded in SiN x matrix by the influence of near-interface oxide traps

“…However, peak C exhibits positive frequency dependent characteristics, which is due to the response of the oxide hole traps in the oxide layer. [20] The influence of oxide hole traps can be further supported by Fig. 6(c).…”

“…This negative frequency dependence of the G-V peak position is the typical characteristics of the admittance peak originated from the interface states between the SiO 2 and the Si substrate. [18][19][20] It should be noted that after electrons start injection, the interface states at SiO 2 /Si-substrate do not influence the electron charging process. However the G-V characteristics of hole charging process are much different from that of the electron charging process.…”

Effect of ion implantation energy for the synthesis of Ge nanocrystals in SiN films with HfO2/SiO2 stack tunnel dielectrics for memory application

“…From Figure 4, it is noteworthy that the same amount of hysteresis and stored charge were obtained in sample A3 irrespective of the measurement frequency. Hence, the capacitance shift can be attributed to the presence of fast traps and/or border traps (near-interfacial traps), which can have a rapid communication with the underlying Si-substrate [29]. The G / w - V curves shift in accordance with the C - V curves.…”