Characterization and modeling of LDMOS transistors on a 0.6 μm CMOS technology

Abstract

Atisrroct -High voltagc integrated circuits (HVIC's) are emerging as viable altcrnatives to discrctc circuits in a wide variety of applications. A commonly used High Voltage component of these circuits is the lateral double diffused MOS transistor (LDMOS). The LDMOS transistor is based an the lightiy doped drain concept. Two of the main objcctives in designing LDMOS devices are to minimize the an-resistance wtiilc still maintaining a high breakdown voltagc. Attempts to model LDMOS devices arc complicatcd by the existcnce of thc ligbtly doped drain and by the cxtcnsion of the gate oxide and polysilicon beyond the channel into this region. This lightly doped drain region can have a large effect on tlie on-resistance, saturation current and feedback capacitance of the dcvice. This paper will present a LDMOS device, consider some of the key specific parameters related to LDMOS devices, discuss a sub-circuit SPICE tnodcl implemented to modcl the LDMOS ctinracteristics and invcstigate some interconnect metellization cffects.

A large-signal model of RF LDMOS with skin effects of power combining structures

“…A large-signal model over the wide range of bias conditions becomes more and more important, since modem PA topologies include a gate bias or supply voltage control scheme and variable load impedance techniques [2], /3]. Previously, RF LDMOS models utilizing the conventional MOSFET models have been reported [4]- [6]. In spite of superiority in scaling, however, the commercial models, such as BSIM3v3, have too many parameters and complex extraction routines, and practically need an additional work to extend their scalability to power transistors, which are wider than B millimeter.…”