No abstract

No abstract

HighVoltage integrated circuits (HVIC's) are emerging as viable alternatives to discrete circuits in a wide variety of applications. A commonly used High Voltage component of these circuits is the lateral double diffused MOS transistor (LDMOS).Modelling the LDMOS transistor is complicated by the existence of the lightly doped drain and by the extension of the gate oxide and polysilicon beyond the channel region into the drain region. This lightly doped drain has a large effect on the feedback capacitance of the device. This paper will discuss the modelling of the capacitances associated with a LDMOS transistor integrated into a conventional 0.6µm CMOS technology.

Atisrroct -High voltagc integrated circuits (HVIC's) are emerging as viable altcrnatives to discrctc circuits in a wide variety of applications. A commonly used High Voltage component of these circuits is the lateral double diffused MOS transistor (LDMOS). The LDMOS transistor is based an the lightiy doped drain concept. Two of the main objcctives in designing LDMOS devices are to minimize the an-resistance wtiilc still maintaining a high breakdown voltagc. Attempts to model LDMOS devices arc complicatcd by the existcnce of thc ligbtly doped drain and by the cxtcnsion of the gate oxide and polysilicon beyond the channel into this region. This lightly doped drain region can have a large effect on tlie on-resistance, saturation current and feedback capacitance of the dcvice. This paper will present a LDMOS device, consider some of the key specific parameters related to LDMOS devices, discuss a sub-circuit SPICE tnodcl implemented to modcl the LDMOS ctinracteristics and invcstigate some interconnect metellization cffects.

AC characterisation of silicon bipolar and BiCMOS processes for RF applications is necessary because of the ever increasing speed of operation of the: bipolar devices. The data acquisition and parameter extraction steps associated with AC characterisation and modelling are time consuming and tedious and cannot easily be implemented as part of standard process monitor measurements.This paper will discuss a methodology for relating the readily available E-Tes t parameter database to the PLC parameters which are more difficult to obtain. The work was done on a 0.6pm BiCMOS process which is suited to mixed mode RF chip designs.