An investigation of on-chip spiral inductors on a 0.6 μm BiCMOS technology for RF applications

Power, J.A.; Kelly, Seán; Griffith, E.C.; O'Neill, M.

doi:10.1109/icmts.1999.766209

Cited by 16 publications

(8 citation statements)

References 7 publications

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“…In Figures 3(a) and (b), the simulated errors e s (11) and e s (21) are less than 5%. Hence, the proposed circuit model can be used to accurately predict the global characteristics of all 63 inductors.…”

Section: A S Parametersmentioning

confidence: 80%

Model description and parameter extraction of on-chip spiral inductors for MMICs

Wang¹,

Pan²,

Li³

et al. 2004

Int J RF and Microwave Comp Aid Eng

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A statistical description of the global performance of on-chip spiral inductors, based on extensive measurement is presented. These inductors were fabricated with different turn numbers or track lengths/track widths, but with the same spacing. From the S parameters measured using a de-embedding technique, the inductance L, Q factor, self-resonance frequency, and figure-of-merit indicator (FMI) of these inductors are determined. Various local scalable formulas are obtained in order to describe the features of these inductors. Based on extensive parametric studies, certain ways to improve these inductor performances can be found.

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Section: A S Parametersmentioning

confidence: 80%

Model description and parameter extraction of on-chip spiral inductors for MMICs

Wang¹,

Pan²,

Li³

et al. 2004

Int J RF and Microwave Comp Aid Eng

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“…This is the reason why all our fabricated inductors have 20 sides. Metal losses decrease if the inductors are fabricated with different metal levels connected by means of vias; in this manner the effective section is increased and, as a result, their associated resistances decrease [10]. For this reason, the inductors were fabricated with the two available metal levels connected in parallel throughout the whole metal length.…”

Section: Experiments Descriptionmentioning

confidence: 99%

Empirical model of the metal losses in integrated inductors

Pino¹,

Garcı́a²,

González³

et al. 2003

SPIE Proceedings

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Integrated inductors are key components in Radio Frequency Integrated Circuits (RFICs) because they are needed in several building blocks, such as voltage-controlled oscillators, low-noise amplifiers, mixers, or filters. The cost reduction, achieved in the circuit assemblage, makes them preferable to Surface Mounted Devices in spite of the different sources of losses that limits the use of integrated inductors; the substrate losses, and the metal losses. We report, in this work, our research in modeling integrated inductors, particularly the losses in the metals. The model is derived from measurements taken from integrated spiral inductors designed and fabricated in a standard silicon process. The measurements reveal that the widely accepted lumped equivalent model does not properly predict the integrated inductor behavior at frequencies above 3 GHz for our technology. We propose a simple modification in the lumped equivalent circuit model: the introduction of an empirical resistor in the port 1-to-port 2 branch of the equivalent circuit. As a result, it will be demonstrated that the integrated inductor behavior is adequately predicted in a wider frequency range than does the conventional model. In addition, the new model is used to build-up an integrated inductor library containing optimized integrated inductors.

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“…Generally the inductors performance is determined by its layout design and its physical characteristics regarding the loss mechanisms like resistive losses of the metal windings and substrate losses. First investigations to improve the Qfactor were focused on optimizing the layout, with satisfying results [1][2][3].…”

Section: Introductionmentioning

confidence: 99%

A New Process for On-Chip Inductors with High Q-Factor Performance

Büyüktas

Koller

Müller

et al. 2010

International Journal of Microwave Science and Technology

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A novel technological method to improve the quality factor (Q) of RF-integrated inductors for wireless applications is presented in this paper. A serious reduction of substrate losses caused by capacitive coupling is provided. This is realised by removing the oxide layers below the coils with optimized underetching techniques. This special etching procedure is used to establish an environment in the inductor substructure with very low permittivity. A set of solid oxide-metal-columns placed below the metal windings stabilize the coil and prevent the hollowed out structure from mechanical collapse. The oxide capacitance is lowered significantly by the reduction of the permittivity from values around 4 to nearly 1. Capacitive coupling losses into substrate are decreasing in the same ratio. The resulting maximum Q-factors of the new designs are up to 100% higher compared to the same devices including the oxide layers but shifted significantly to higher frequencies. Improvements of Q from 10 up to 15 have been obtained at a frequency of 3 GHz for a 2.2 nH inductor with an outer diameter of 213 m. The resonance frequency () and frequency at maximum Q () are shifted to higher frequencies, caused by the shrunk total capacitance of the structure. This enables the circuit designer to use the inductors for applications working at higher frequencies. Coils with different layouts and values for inductance (L) were verified and showed similar results.

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An investigation of on-chip spiral inductors on a 0.6 μm BiCMOS technology for RF applications

Cited by 16 publications

References 7 publications

Model description and parameter extraction of on-chip spiral inductors for MMICs

Model description and parameter extraction of on-chip spiral inductors for MMICs

Empirical model of the metal losses in integrated inductors

A New Process for On-Chip Inductors with High Q-Factor Performance

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