Statistical modeling for a 0.6 μm BiCMOS technology

Power, J.A.; Kelly, Seán; Griffith, E.C.; Doyle, D.; O'Neill, M.

doi:10.1109/bipol.1997.647348

Cited by 5 publications

(3 citation statements)

References 4 publications

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“…[6]- [10]): model parameters of a single device are extracted for many dies and wafers. Then, this variation in model parameters is used for MCS.…”

Section: Monte Carlo Simulation (Mcs) Based Methodsmentioning

confidence: 99%

“…Hence, the task is to determine the TP standard deviation vector at from ap. Assuming that the tolerance ranges in SM are fairly small, the propagation of variances approach can be used, which results in a linear equation system relating the PCM variances to the TP variances, 2 2 csp Aptat (10) The elements of the matrix At correspond to the square of the derivatives of the PCMs with respect to the TPs. These derivatives are taken at the nominal values, using the analytical equations presented earlier.…”

Section: Relation Between Compact Models and Pcmsmentioning

confidence: 99%

“…1 1][3][10]. The desired model parameter subset now consists of only those model parameters (the dominant parameters), that are responsible for, e.g., 80% or more of the variations in the observation variables.…”

mentioning

confidence: 99%

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Statistical modeling of high-frequency bipolar transistors

Schröter

Wittkopf²,

Kraus³

Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, 2005.

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An overview on existing approaches for statistical modeling of bipolar transistors is given with emphasis on practically feasible statistical simulation of analog/h.f. circuits. A suitable approach is outlined and applied to both device simulation and experimental fab data. I IntroductionToday's competitive semiconductor market demands a reduction of design and mask cost by first pass success for even high-frequency (h.f.) analog circuits. In addition, the demand for early market entry is forcing co-development of process and circuits (concurrent engineering). Thus, predictive modeling strategies have to be applied to provide early design kits with realistic simulation-based compact models.Variations in processing conditions during wafer fabrication cause unavoidable manufacturing tolerances, which are typically of random nature in a production process. One can distinguish between intra-die and interdie variations (e.g. j1][2][3]). The latter include variations that occur from die-to-die on a single wafer, from wafer-towafer within a single lot and from lot-to-lot over time (possibly due to shifting process conditions). Compared to these, intra-die variations occur only over small distances within a die and are thus much smaller.Tolerances in circuit manufacturing affect the yield of a product. They can be divided into parametric variations and into catastrophic failures. The latter, characterized by a non-functional circuit, need to be resolved by changing the processing procedures (incl. equipment, materials) or the design itself. In contrast, parametric variations are fundamentally unavoidable. Hence, they can only be minimized to a certain extent and subject to cost constraints. Parametric variations lead to functional yield, in which circuits are fundamentally functional but their electrical performance parameters may not meet the specifications, and to parametric yield, in which circuit performance varies within the specification limits.The ultimate goal is to optimize circuit yield while at the same time meeting the given circuit performance specifications; this goal is often referred to as yield optimization [1][2][3]. To allow the design of manufacturable circuits, the associated design tools and methodologies have to include process tolerances; the corresponding overall strategy is often called design for manufacturability (DfM) [3]; for instance, one of the strategies (design centering) aims at making the circuit behavior as insensitive to process variations as possible (e.g. [5][6]). DfM attempts to incorporate process tolerances into the design methodology, partially by using accurate simulation. To meet circuit performance specifications in a given process -often called (electrical) circuit optimization-, usually only the device layout is varied intentionally, while the vertical device structure (incl. dimensions and doping) is assumed to be unchanged. Compared to electrical optimization, yield optimization requires to include process tolerances in layout and device structure. Work on design centeri...

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“…[6]- [10]): model parameters of a single device are extracted for many dies and wafers. Then, this variation in model parameters is used for MCS.…”

Section: Monte Carlo Simulation (Mcs) Based Methodsmentioning

confidence: 99%

Section: Relation Between Compact Models and Pcmsmentioning

confidence: 99%

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et al.

Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition

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Statistical modeling for a 0.6 μm BiCMOS technology

Cited by 5 publications

References 4 publications

Statistical modeling of high-frequency bipolar transistors

Statistical modeling of high-frequency bipolar transistors

RF and Other Compact Model Applications

Analog IP testing: diagnosis and optimization

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