Characterization and modeling of on-chip via stacks for RF-CMOS applications

Abstract

This work proposes an experiment-based characterization and modeling approach for interconnection channels including via stacks as vertical transitions. A daisy chain structure implemented in a 0.18 µm RFCMOS process is used for developing and verifying the validity of the proposal. The usefulness of the models is shown by assessing the impact of the vias in a practical resonant rotary traveling wave oscillator (RTWO). The oscillation frequency of the RTWO is reduced 13.7% when the via stack models are included.