Characterization and modeling of second breakdown in NMOST's for the extraction of ESD-related process and design parameters

Suppression and origin of soft ESD failures in a submicron CMOS process

“…Leaving out the LDD reduces this subsurface effect considerably. The existence of such a narrow region was expected from the studies in [2]. Here we see where it is and that we are dealing with two separate mechanisms: one deep in the junction and one just below the surface.…”

“…By now, the concepts of second breakdown should be familiar for process development and protection design. Soft failures, however, have received attention but are not fully understood yet I- [1][2][3]. Reduced input leakage specifications increase the need for a better understanding of the phenomenon even more.…”

“…Moreover, the effect of simple drain variations, like omitting the LDD implantation, or overdoping the LDD [4,2,3] is studied. Omitting the LDD has the advantage that the process remains the same.…”

ESD performance of 65nm partially depleted n and p channel SOI MOSFETs

“…This figure shows that the higher power dissipation occurs in GNS devices due to the higher current handling capability than similarly sized GS device. In the figure, the experimental power-to-failure profiles for GS and GNS SOI nMOSFETs are also compared with the analytical thermal model presented by Amerasekera et al [12] for the bulk MOSFETs. The model assumes (a) a rectangular-box region of device heating in the drain-side junction depletion region of a MOSFET, (b) constant temperature boundary conditions on all sides of the box (an infinite heat sink) and, (c) no heating outside the box.…”

Thyristor Input-Protection Device Suitable for CMOS RF IC?s

“…3, the 2nd breakdown [7] occurs when the drain current is about 6 × 10 −4 A/µm, and the required drain-source voltage is reduced further to cause device failures relating drain-contact melting in real devices. The protection devices should not enter the 2nd breakdown regime during any ESD events.…”