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Band-gap engineering using SiGe channels to reduce the threshold voltage (V TH ) in p-channel MOSFETs has enabled a simplified gate-first high-κ/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with T inv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.Introduction:

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A SEM-EBIC minority-carrier lifetime-measurement method is described, whereby an arrangement is used such that the electron beam is incident normal to the charge-collecting barrier; the barrier may be either that of a Schottky diode or of a very shallow p-n junction. The beam is positioned at a constant point over the barrier, and the lifetime is found by rapidly switching off the beam and analysing the resulting EBIC time decay. In many practical cases this decay is given by I(t) varies as (exp(-t/ tau ))/t1/2 where tau is the lifetime and I(t) the EBIC at time t after the beam is switched off, and therefore plotting ln(It1/2) versus t results in a straight line from the slope of which tau can be obtained.