Characterization and Modeling of Self-Heating in Nanometer Bulk-CMOS at Cryogenic Temperatures

Abstract

This work presents a self-heating study of a 40nm bulk-CMOS technology in the ambient temperature range from 300 K down to 4.2 K. A custom test chip was designed and fabricated for measuring both the temperature rise in the MOSFET channel and in the surrounding silicon substrate, using the gate resistance and silicon diodes as sensors, respectively. Since self-heating depends on factors such as device geometry and power density, the test structure characterized in this work was specifically designed to resemble actual devices used in cryogenic qubit control ICs. Severe self-heating was observed at deep-cryogenic ambient temperatures, resulting in a channel temperature rise exceeding 50 K and having an impact detectable at a distance of up to 30 µm from the device. By extracting the thermal resistance from measured data at different temperatures, it was shown that a simple model is able to accurately predict channel temperatures over the full ambient temperature range from deep-cryogenic to room temperature. The results and modeling presented in this work contribute towards the full selfheating-aware IC design-flow required for the reliable design and operation of cryo-CMOS circuits.

Superconducting routing platform for large-scale integration of quantum technologies

“…read-out circuits. Moreover, the choice of materials and technologies included in the interposer provide solutions to thermally decoupled the quantum and cryo-CMOS chips, protecting the qubits from cryo-CMOS self-heating [20,21] to limit decoherence mechanisms.…”