Characterization and modeling of transient device behavior under CDM ESD stress

Study of CDM specific effects for a smart power input protection structure

“…Device physical effects reported by Willemen et al [13] strongly influence the device behavior during fast transients. The transient device series resistance can increase up to one order of magnitude during the fast rising slopes of CDM events.…”

“…Hence, we determined the transient forward and reverse behavior of the n + -buried layer/p-substrate junction with vf-TLP measurements and TLP measurements using an equivalent buried layer/substrate test structure. Parameters for the forward behavior of the pn-junction were extracted for a model including the forward recovery effect as reported in [13]. Since high voltages occurred across the parasitic pn-junctions during the CDM circuit simulation, which exceeded even the high breakdown voltage V BD % 110 V of the n + -buried layer/substrate junction, the junction breakdown voltage and the substrate/buried layer series resistance were determined and added to the circuit models.…”

“…the forward recovery effect of diodes or the transit time of bipolar transistors, influence the turn-on behavior of the protection device and therefore the series resistance of the structure during a CDM event [13]. Hence, the transient high-current parameters were extracted for a compact model including the transient effects relevant for the CDM time domain.…”

Advances in Modeling and Suppression Methods of EMI in Power Electronic Converters of Third-Generation Semiconductor Devices

“…If the working conditions are inconsistent with the parameter-fitting conditions, the accuracy of the model will be significantly reduced. Willemen and Hsu [33,34] proposed an analytical model of MOSFET that used the parameters obtained from the device data tables and the parasitic parameters of the external circuit to simulate the high-frequency behavior of MOSFET. Y Yuan [35] proposed a MOSFET segmented behavior model that prioritizes runtime performance and convergence behavior, and is thus suitable for computer-based simulation analysis.…”

A Study of Transient Voltage Peaking in Diode-Based ESD Protection Structures in 28nm CMOS

“…Typically, a diode string or a DTSCR ESD protection structure utilizes either STI-diode or gated-diode to control ESD triggering. However, it is reported that, under CDM ESD stressing that features extremely fast pulse rise time (t r ∼200ps) and very short pulse duration (t d1 ∼1ns for the first peak) [13], transient voltage peaking right before the ESD triggering may occur that causes early ESD failures due to the delay in ESD triggering and rupture in the thin gate oxide [8]- [12]. Transient voltage peaking becomes a major CDM ESD protection design problem for ICs at sub-28nm nodes, which must be thoroughly understood.…”