Characterization and Physical Origin of Fast Vth Transient in NBTI of pMOSFETs with SiON Dielectric

Chen, Shen; Li, M.-F.; Foo, C.E.; Yang, Tianzhi; Huang, Daming; Yap, Andrew; Samudra, Ganesh S.; Yeo, Yee-Chia

doi:10.1109/iedm.2006.346776

Cited by 139 publications

(136 citation statements)

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“…1) clearly suggest presence or absence of large hole trapping (ΔV h ) component in N-related traps [4], [11], particularly at early stress time. As ΔV h saturates fast and has weaker T activation [3]- [5], [11], [12], it causes lower n ( Fig. 2) and E A (Fig.…”

Section: Resultsmentioning

confidence: 99%

“…UF-OTF can be used to determine degradation from very short (approximately microseconds) to long stress time, although it requires postprocessing to convert I DLIN degradation to V T shift as discussed in [12]. However, while NBTI in SiON p-MOSFETs has been studied using UF-SMS or UF-OTF techniques [4], [11], [13], to the best of our knowledge, most studies of NBTI in high-k p-MOSFETs [5]- [8] were done using conventional SMS and calls for a reevaluation by UF methods, particularly to probe the degradation at early stress time and to have recovery-artifact-free degradation at longer stress time.…”

Section: Introductionmentioning

confidence: 99%

“…It is now well known that defects generated during NBT stress recovers after stress is removed, and conventional stress-measure-stress (SMS) methods suffer from recovery-related artifacts that result in incorrect degradation magnitude, time, and temperature (T ) dependence of NBTI [9], [10]. To overcome this issue, ultrafast (UF) SMS [11] and UF on-the-fly (UF-OTF) I DLIN [4] techniques were developed. UF-SMS provides direct estimation of V T shift, although it cannot be used to measure degradation at very short stress time.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Comparative NBTI Study of $\hbox{HfO}_{2}$, $\hbox{HfSiO}_{x}$, and SiON p-MOSFETs Using UF-OTF $I_{\rm DLIN}$ Technique

Deora

Maheta

Bersuker

et al. 2009

IEEE Electron Device Lett.

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Abstract-The time, temperature, and oxide-field dependence of negative-bias temperature instability is studied in HfO 2 /TiN, HfSiO x /TiN, and SiON/poly-Si p-MOSFETs using ultrafast on-the-fly I DLIN technique capable of providing measured degradation from very short (approximately microseconds) to long stress time. Similar to rapid thermal nitrided oxide (RTNO) SiON, HfO 2 devices show very high temperature-independent degradation at short (submilliseconds) stress time, not observed for plasma nitrided oxide (PNO) SiON and HfSiO x devices. HfSiO x shows lower overall degradation, higher long-time power-law exponent, field acceleration, and temperature activation as compared to HfO 2 , which are similar to the differences between PNO and RTNO SiON devices, respectively. The difference between HfSiO x and HfO 2 can be attributed to differences in N density in the SiO 2 IL of these devices.Index Terms-Activation energy, field acceleration, high-k dielectric, hole trapping, interface traps, negative-bias temperature instability (NBTI), plasma oxynitride, p-MOSFET, thermal oxynitride, time exponent.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Comparative NBTI Study of $\hbox{HfO}_{2}$, $\hbox{HfSiO}_{x}$, and SiON p-MOSFETs Using UF-OTF $I_{\rm DLIN}$ Technique

Deora

Maheta

Bersuker

et al. 2009

IEEE Electron Device Lett.

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“…This is due to the introduction of surface channel p-MOSFETs for analog circuits and the scaling of gate oxides below 2 nm for digital circuits, without proportionate scaling of supply voltages. In particular, the incorporation of nitrogen in sub-2-nm gate oxides (to prevent boron penetration and reduce gate leakage) has presently made NBTI the most crucial reliability concern [10]- [27].…”

Section: Introductionmentioning

confidence: 99%

Defect Generation in p-MOSFETs Under Negative-Bias Stress: An Experimental Perspective

Mahapatra

Alam

2008

IEEE Trans. Device Mater. Relib.

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“…During the recovery phase a positive electric field is placed accross the oxide layer. The field removes the inverted channel and hydrogen is free to reconnect with the available silicon by annealing [6,7,8,9,10]. This process, much like stressing, can be exacerbated by increased temperature.…”

Section: Overview Of Nbti and Related Workmentioning

confidence: 99%

A Multi-Level Approach to NBTI Mitigation in Processors

Siddiqua

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We are in the era of multicore processors and it is expected that the number of the processing cores on a chip will steadily increase over the next decade, driven by Moore's Law. While technology scaling has benefitted high performance, the scaling has a dark side too: a degradation in the reliability of silicon devices. Processors have become highly susceptible to a variety of reliability problems in silicon, such as particle induced soft errors and hard errors. Therefore, processors have to be designed to provide adequate protection against these reliability problems while maintaining high performance and energy efficiency. Designing a reliable computer system is a large and complex multi-dimensional and multi-level problem, comprising of different hardware blocks, reliability phenomena, design layers, metrics, and optimization techniques. This dissertation considers a key emerging reliability phenomenon: Negative Bias Temperature Instability (NBTI). This dissertation develops NBTI mitigation techniques for the logic and memory structures in the processor that impose very little performance, power, and area overheads. This research also creates the foundation for understanding NBTI in the context of one other important processor reliability problem: process variations.

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Characterization and Physical Origin of Fast Vth Transient in NBTI of pMOSFETs with SiON Dielectric

Cited by 139 publications

References 2 publications

A Comparative NBTI Study of $\hbox{HfO}_{2}$, $\hbox{HfSiO}_{x}$, and SiON p-MOSFETs Using UF-OTF $I_{\rm DLIN}$ Technique

A Comparative NBTI Study of $\hbox{HfO}_{2}$, $\hbox{HfSiO}_{x}$, and SiON p-MOSFETs Using UF-OTF $I_{\rm DLIN}$ Technique

Defect Generation in p-MOSFETs Under Negative-Bias Stress: An Experimental Perspective

A Multi-Level Approach to NBTI Mitigation in Processors

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