Characterization of 4 K CMOS Devices and Circuits for Hybrid Josephson-CMOS Systems

Abstract

Characterization and modeling of CMOS devices at 4.2 K are carried out in order to simulate low-temperature operation of CMOS circuits for Josephson-CMOS hybrid systems. CMOS devices examined in this study have been fabricated by using 0.18 m, 0.25 m, and 0.35 m commercial CMOS processes. Their static I-V characteristics and capacitances are measured at 4.2 K to establish the low-temperature device model based on the BSIM3 SPICE model. The propagation delays of CMOS inverters measured by using ring oscillators agree well with the simulation results. The experimental results indicate about 40% speedup from 300 K to 4.2 K. A three-transistor DRAM cell for a Josephson-CMOS hybrid memory is also investigated at low temperature. The temperature dependence of the retention time shows an exponential increase at low temperatures. Based on the lowtemperature CMOS device model, we have developed short-delay CMOS amplifiers, which would amplify a 40 mV voltage input to CMOS voltage level with the propagation delay of about 100 ps, assuming the use of a 0.18 m CMOS process. We have measured the propagation delay of the CMOS amplifier by using a single-flux-quantum (SFQ) delay measurement system. This is a complete demonstration of the signal exchanges between SFQ and CMOS circuits at 4.2 K.

Access time measurement of 64-kb Josephson-CMOS hybrid memories using SFQ time-to-digital converter

“…The access time of about 1.2 ns is obtained and almost agrees with a simulation result based on our low-temperature CMOS device model [4]. However, double peaks appear in the histogram of access time measurements [6].…”

“…Fig. 1 (b) shows a block diagram of the access time measurement system [4]. An SFQ time-to-digital converter (TDC) was used to measure the access time of the hybrid memory in time resolution of several tens of picosecond.…”

“…One potential application of the hybrid systems is a Josephson-CMOS hybrid memory [2,3,4,5,6]. In the hybrid memory, memory cells and address decoders are made up with CMOS circuits, while Josephson current-sense circuits are used to detect small bit-line current with short delay.…”

The Evolution of Theory on Drain Current Saturation Mechanism of MOSFETs from the Early Days to the Present Day

“…As shown in Fig.17, v sat_eff increases when temperature decreases, resulting in a better I on performance at very low temperature. This shows that equation (19) is able to explain the I on enhancement at liquid helium temperature (Chou et al, 1985;Ghibaudo & Balestra, 1997;Yoshikawa et al, 2005). www.intechopen.com…”

“…If equations (10) and (11) are correct, MOS transistors will function very poorly when the temperature is lowered from room temperature to very low temperature such as liquid helium temperature. However, there are numerous reports that MOS transistors and CMOS integrated circuits can function quite well at the liquid helium temperature (Chou et al, 1985;Ghibaudo & Balestra, 1997;Yoshikawa et al, 2005). Hence, there is a need to modify Lundstrom's 1997 theory.…”