Characterization of a RISC-V Microcontroller Through Fault Injection

Asciolla, Dario; Dilillo, Luigi; Santos, Douglas A.; Melo, Douglas Rossi de; Menicucci, A.; Ottavi, Marco

doi:10.1007/978-3-030-37277-4_11

Cited by 6 publications

(5 citation statements)

References 5 publications

(4 reference statements)

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“…Other research has conducted extensive fault investigation of the CV32E40P core used in the cluster based on fault injection [6], showing that many injected faults do not affect the program execution, with the most critical module being the controller module. As only 12% of injected errors lead to corrective action, this confirms the results of Asciolla et al [6], where 44%-100% of injected errors lead to no correction, depending on the component. 4.5 Recovery Use-case Analysis: Satellite Onboard Image Processing One of the most common use cases of multi-core computing systems for S-CPS applications is using such devices for satellite onboard image processing.…”

Section: Reliability Assessmentmentioning

confidence: 99%

Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space

Rogenmoser¹,

Tortorella²,

Rossi³

et al. 2023

Preprint

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Space Cyber-Physical Systems (S-CPS) such as spacecraft and satellites strongly rely on the reliability of onboard computers to guarantee the success of their missions. Relying solely on radiation-hardened technologies is extremely expensive, and developing inflexible architectural and microarchitectural modifications to introduce modular redundancy within a system leads to significant area increase and performance degradation as well. To mitigate the overheads of traditional radiation hardening and modular redundancy approaches, we present a novel Hybrid Modular Redundancy (HMR) approach, a redundancy scheme that features a cluster of RISC-V processors with a flexible on-demand dual-core and triple-core lockstep grouping of computing cores with runtime split-lock capabilities. Further, we propose two recovery approaches, software-based and hardware-based, trading off performance and area overhead. Running at 430 MHz, our fault-tolerant cluster achieves up to 1160 MOPS on a matrix multiplication benchmark when configured in non-redundant mode and 617 and 414 MOPS in dual and triple mode, respectively. A software-based recovery in triple mode requires 363 clock cycles and occupies 0.612 mm 2 , representing a 1.3% area overhead over a non-redundant 12-core RISC-V cluster. As a high-performance alternative, a new hardware-based method provides rapid fault recovery in just 24 clock cycles and occupies 0.660 mm 2 , namely ∼9.4% area overhead over the baseline non-redundant RISC-V cluster. The cluster is also enhanced with split-lock capabilities to enter one of the available redundant modes with minimum performance loss, allowing execution of a safety-critical portion of code with 310 and 23 clock cycles overhead for entry and exit, respectively. The proposed system is the first to integrate these functionalities on an open-source RISC-V-based compute device, enabling finely tunable reliability vs. performance trade-offs.

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Section: Reliability Assessmentmentioning

confidence: 99%

Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space

Rogenmoser¹,

Tortorella²,

Rossi³

et al. 2023

Preprint

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“…Once an error propagates to the core interface, a mismatch is detected and the re-synchronization is successfully able to correct the faulty register. As analyzed in more detail in [10], not all faults within a core cause a noticeable failure of the system, as many of the errors are masked.…”

Section: Fault Injectionmentioning

confidence: 99%

On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster

Rogenmoser

Wistoff

Vogel³

et al. 2022

2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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With the shrinking of technology nodes and the use of parallel processor clusters in hostile and critical environments, such as space, run-time faults caused by radiation are a serious cross-cutting concern, also impacting architectural design. This paper introduces an architectural approach to run-time configurable soft-error tolerance at the core level, augmenting a six-core open-source RISC-V cluster with a novel On-Demand Redundancy Grouping (ODRG) scheme. ODRG allows the cluster to operate either as two fault-tolerant cores, or six individual cores for high-performance, with limited overhead to switch between these modes during run-time. The ODRG unit adds less than 11% of a core's area for a three-core group, or a total of 1% of the cluster area, and shows negligible timing increase, which compares favorably to a commercial state-of-the-art implementation, and is 2.5× faster in fault recovery re-synchronization. Furthermore, when redundancy is not necessary, the ODRG approach allows the redundant cores to be used for independent computation, allowing up to 2.96× increase in performance for selected applications.

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“…Once an error propagates to the core interface, a mismatch is detected and the re-synchronization is successfully able to correct the faulty register. As analyzed in more detail in [21], not all faults within a core cause a noticeable failure of the system, as many of the errors are masked.…”

Section: Fault Injectionmentioning

confidence: 99%

On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster

Rogenmoser¹,

Wistoff²,

Vogel³

et al. 2022

Preprint

View full text Add to dashboard Cite

With the shrinking of technology nodes and the use of parallel processor clusters in hostile and critical environments, such as space, run-time faults caused by radiation are a serious cross-cutting concern, also impacting architectural design. This paper introduces an architectural approach to run-time configurable soft-error tolerance at the core level, augmenting a six-core open-source RISC-V cluster with a novel On-Demand Redundancy Grouping (ODRG) scheme. ODRG allows the cluster to operate either as two fault-tolerant cores, or six individual cores for high-performance, with limited overhead to switch between these modes during run-time. The ODRG unit adds less than 11% of a core's area for a three-core group, or a total of 1% of the cluster area, and shows negligible timing increase, which compares favorably to a commercial state-ofthe-art implementation, and is 2.5× faster in fault recovery re-synchronization. Furthermore, unlike other implementations, when redundancy is not necessary, the ODRG approach allows the redundant cores to be used for independent computation, allowing up to 2.96× increase in performance for selected applications.

show abstract

Characterization of a RISC-V Microcontroller Through Fault Injection

Cited by 6 publications

References 5 publications

Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space

Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space

On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster

On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster

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