Characterization of an Etch Profile at a Wafer Edge in Capacitively Coupled Plasma

Seong, Inho; Lee, Jinho; Kim, Sijun; Lee, Youngseok; Cho, Chul‐Hee; Lee, Jangjae; Jeong, Wonnyoung; You, Yebin; You, S. J.

doi:10.3390/nano12223963

Cited by 6 publications

(5 citation statements)

References 33 publications

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“…Short-loop wafers that only contained TSVs etched into Si wafers coated with only a dielectric layer, but no other layers or patterning, as well as wafers with full back-end processing, were investigated. Asymmetric processing can occur during the TSV RIE process, especially towards the wafer edge [6]. Figure 2 depicts the resulting TSV geometry resulting from asymmetric processing.…”

Section: Methodsmentioning

confidence: 99%

Spectral interferometry for TSV metrology in chiplet technology

Schoeche,

Schmidt,

Han

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

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Comprehensive through-silicon-via (TSV) characterization, including grind side measurements, is critical to ensure device reliability in chiplet technology. Here we report on TSV metrology using spectral interferometry (SI), which is used to acquire absolute phase information of polarized and broad-band light interacting with a sample. This phase information can be translated into the optical path length of the partial beams traveling within the structure. We utilize the spatial separation of peaks related to light reflected from the top surface and the surface of interest to directly measure the TSV depth after reactive ion etching as well as the reveal height on the grind side, without modeling and even in the presence of multilayers or surrounding patterning. Polarization-dependent SI measurements enable the quantification of asymmetry at the bottom of the TSVs not visible in top-down CD measurements. SI is robust and fast and unveils novel information in TSV metrology not accessible with established in-line metrology techniques.

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Section: Methodsmentioning

confidence: 99%

Spectral interferometry for TSV metrology in chiplet technology

Schoeche,

Schmidt,

Han

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

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“…The objective with L 2 regularization is argmin f, g L (x, r (x)) + λ ∂f (x) ∂x 2 F . (7) This regularization makes the encoder less sensitive to small perturbations of the input data, resulting in the latent representation being locally invariant in many directions of change of the input data [74]. Its effect can be viewed as the contraction of the input space.…”

Section: Appendix C Simple Variants Of Ae Model With Regularizationsmentioning

confidence: 99%

“…For example, complex 3D structures with HAR patterns are commonly implemented in memory devices whose fabrication requires advanced plasma techniques, which presents many challenges in controlling the process conditions to achieve uniform profiles with a high yield for the mass production of semiconductor devices. Typically, highly collimated ions are needed to produce fine HAR contact holes during plasma processing [6,7]. To guarantee the precise shape of the HAR pattern, the effects of localized disturbances in the process should be considered, such as variations in the mask pattern shape [4,8], sheath curvature at the wafer edge [5,7], and the local charging effect inside the trench [9,10], as these disturbances significantly influence the trajectories of energetic ions, thus altering the etched profile substantially.…”

Section: Introductionmentioning

confidence: 99%

“…Typically, highly collimated ions are needed to produce fine HAR contact holes during plasma processing [6,7]. To guarantee the precise shape of the HAR pattern, the effects of localized disturbances in the process should be considered, such as variations in the mask pattern shape [4,8], sheath curvature at the wafer edge [5,7], and the local charging effect inside the trench [9,10], as these disturbances significantly influence the trajectories of energetic ions, thus altering the etched profile substantially.…”

Section: Introductionmentioning

confidence: 99%

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Deep neural network-based reduced-order modeling of ion–surface interactions combined with molecular dynamics simulation

Kim¹,

Bae²,

Jeong³

et al. 2023

J. Phys. D: Appl. Phys.

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With the advent of complex and sophisticated architectures in semiconductor device manufacturing, atomic-resolution accuracy and precision are commonly required for industrial plasma processing. This demands a comprehensive understanding of the plasma–material interactions—particularly for forming fine high-aspect ratio (HAR) feature patterns with sufficiently high yield in wafer-level processes. In particular, because the shape distortion in HAR pattern etching is attributed to the deviation of the energetic ion trajectory, the detailed ion–surface interactions need to be thoroughly investigated. In this study, molecular dynamics (MD) simulations were utilized to obtain a fundamental understanding of the collisional nature of accelerated Ar ions on the fluorinated Si surface that may appear on the sidewall of the HAR etched hole. High-fidelity data for ion–surface interaction features representing the energy and angle distributions (EADs) of sputtered atoms for varying degrees of surface F coverage and ion incident angles were obtained via extensive MD simulations. A deep learning-based reduced-order modeling (DL-ROM) framework was developed for efficiently predicting the characteristics of the ion–surface interactions. In the ROM framework, a conditional variational autoencoder (CVAE) was implemented to obtain regularized latent representations of the distributional data with the condition of the governing factors of the physical system. The proposed ROM framework accurately reproduced the MD simulation results and significantly outperformed various DL-ROMs, such as autoencoder (AE), sparse AE (SAE), contractive AE (CAE), denoising AE (DAE), and variational AE (VAE). From the inferred features of the sputtering yield and EADs of sputtered/scattered species, significant insights can be obtained regarding the ion interactions with the fluorinated surface. As the ion incident angle deviated from the glancing-angle range (incident angle > 80°), diffuse reflection behavior was observed, which can substantially affect the ion transport in the HAR patterns. Moreover, it was hypothesized that a shift in sputtering characteristics occurs as the surface F coverage varies, based on the inferred EADs. This conjecture was confirmed through detailed MD simulations that demonstrated the fundamental relationship between surface atomic conformations and their sputtering behavior. Combined with additional atomistic-scale investigations, this framework can provide an efficient way to reveal various fundamental plasma–material interactions which are highly demanded for the future development of semiconductor device manufacturing.

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“…The tilted etch profiles manifest themselves in potential overlay issues concerning features at the bottom. For a more detailed description of the effect see reference [5]. The spatial characteristics of this variability mechanism are that it occurs at the extreme wafer edge (<100 mm from the wafer edge) and the overlay signatures are radially symmetric.…”

Section: Epe Modeling Using Physical Mechanismsmentioning

confidence: 99%

Multi-metrology: towards parametric yield predictions beyond EPE

Zach¹,

Cancheepuram²,

Sah

et al. 2023

Metrology, Inspection, and Process Control XXXVII

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Variability control has been a key enabler for achieving continuing technology shrinks in both logic as well as DRAM. With ever-tightening requirements, simple one-dimensional metrology and control aspects, i.e. separate variability control for CD and overlay, are no longer adequate [1]. To improve on this approach, simultaneous control of more than one parameter has been discussed to minimize the parametric yield impact. One such example is to improve edge placement error (EPE), a metric where overlay and CD metrology are combined [1]. In this work, we will revisit the EPE concept from the perspective of using established methodologies used in yield modeling. Rather than starting with a litho-centric approach, we cast the problem as a parametric yield loss mechanism driven by patterning parameters. In contrast to the widely disseminated EPE budget that originates from a patterning process-centric view, we introduce a modified analysis framework. The development of the approach discussed in this work starts with well-known yield engineering approaches rooted in defectivity modeling/statistics. It then proceeds towards quantifying and thus allowing a statistically sound quantification and thus prioritization of patterning (i.e. litho or post etch) improvements based on their impact on the yield loss Pareto. In doing so, the new formalism sheds light on what aspects of the EPE distribution most prominently affects yield loss. It also reveals that the ratio of potentially failing instances with a die and the max number of fails tolerable before the die fails plays a role in formulating any kind of budget approach. When putting our concepts to the test we discovered that there is yet another significant contributor affecting the acceptable variation range. We find that the “rigid structure approach”, an inherent assumption in any budget breakdown, and feature-to-feature interactions drive a significant reduction of the available processing tolerances. We attribute this mechanism to the 3D aspects of the patterning process and present a model that can handle the interactions. Finally, we discuss our approach to addressing the fact that process variability happens on length scales that cover several orders of magnitude. We developed a physical budget breakdown that attempts to optimize the tradeoff between sample size and the ability to capture variability over this wide range of length scales. We will postpone our discussion on other sampling-related topics. The question of how one obtains all required metrology data on one wafer in a manufacturing environment will be addressed in a future publication.

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Characterization of an Etch Profile at a Wafer Edge in Capacitively Coupled Plasma

Cited by 6 publications

References 33 publications

Spectral interferometry for TSV metrology in chiplet technology

Spectral interferometry for TSV metrology in chiplet technology

Deep neural network-based reduced-order modeling of ion–surface interactions combined with molecular dynamics simulation

Multi-metrology: towards parametric yield predictions beyond EPE

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