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This paper presents a feasibility study on patterning the critical layers of Bit-Line Periphery (BLP) and Storage Node Landing Pad (SNLP) for advanced 10nm node DRAM with sub-40nm pitch using a single EUV patterning. Source Mask Optimization (SMO) and aerial image-based Optical Proximity Correction (OPC) were initially conducted to classify image data and identify potential weak points of the primary patterning mask. A secondary patterning mask was then produced based on the resist model and design split using the obtained data on the primary mask to address these issues. Results obtained through PV-band and intensity analysis of each area in simulation, as well as ADI and AEI (After Etch Inspection) using photoresists with 2 kinds of different tones (PTD CAR and Spin-on MOR PR), demonstrated the feasibility of patterning BLP and SNLP with a single EUV mask. Additionally, Process Window Discovery (PWD) wafers were fabricated to analyze and review process margins and potential weak points through KLA inspection for systematic patterning defectivity. Furthermore, our experiments confirmed that the performance of EUV patterning with DRAM BLP/SNLP layer can be expected to improve by reducing the dose (in mJ/cm2) by approximately 30% using a secondary mask by retarget bias split and resist model OPC.

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