Characterization of Collector‐Emitter Leakage in Self‐Aligned Double‐Poly Bipolar Junction Transistors

Abstract

Collector‐emitter leakage (CE leakage) is an inherent problem in bipolar technology. In this paper, we have investigated a variety of process steps that improve the CE leakage performance in a self‐aligned double poly poly‐emitter bipolar integrated circuit process. Stress generated from deep trench processing and damage from reactive ion etching (RIE) are identified as major sources of CE leakage. Lack of substrate gettering capabilities, stress generated from furnace operations as well as inadequate prevention of device punch‐through phenomenon are also shown to create CE leakage. Several experiments that identify the CE leakage sources and improve circuit performance are presented.